Three dimensional logic circuit

1. An integrated circuit, comprising:

a multi-bit flip-flop circuit with a plurality of single bit flip-flop circuits, each single bit flip-flop circuit of the plurality of single bit flip-flop circuits comprises a clocked portion driven by a clock signal and a non-clocked portion;

a common clock circuit, each of the clocked portions of the plurality of single bit flip-flop circuits being connected to the common clock circuit;

a common scan circuit, each of the non-clocked portions of the plurality of single bit flip-flop circuits are connected to the common scan circuit;

wherein the clocked portions of the plurality of single bit flip-flop circuits are in a first tier and each of the clocked portions comprises a master latch component, a slave latch component, and a plurality of transmission gates; and

wherein the non-clocked portions of the plurality of single bit flip-flop circuits are in a second tier positioned above the first tier and each of the non-clocked portions comprises a data input, an inverted data input, a scan input, and a plurality of input/output transistors.

2. The integrated circuit of claim 1 , wherein the multi-bit flip-flop circuit is a four bit flip-flop circuit.

3. The integrated circuit of claim 2 , wherein the plurality of single bit flip-flop circuits comprises a first single bit flip-flop circuit directly coupled to the common clock circuit, a second single bit flip-flop circuit coupled to the first single bit flip-flop circuit, a third single bit flip-flop circuit coupled to the second single bit flip-flop circuit, and a fourth single bit flip-flop circuit coupled to the third single bit flip-flop circuit and directly coupled to the common clock circuit.

4. The integrated circuit of claim 3 , wherein the first single bit flip-flop circuit and the fourth single bit flip-flop circuit are directly coupled to the common scan circuit.

5. The integrated circuit of claim 4 , wherein the first single bit flip-flop circuit has an inverted output directly coupled to the common scan circuit.

6. The integrated circuit of claim 5 , wherein an inverted input of the first single bit flip-flop circuit is directly coupled to an inverted output of the second single bit flip-flop circuit.

7. The integrated circuit of claim 6 , wherein an inverted input of the second single bit flip-flop circuit is directly coupled to an inverted output of the third single bit flip-flop circuit.

8. The integrated circuit of claim 7 , wherein an inverted input of the third single bit flip-flop circuit is directly coupled to an inverted output of the fourth single bit flip-flop circuit.

9. The integrated circuit of claim 8 , further comprising routing pathways coupling the first tier to the second tier.

10. An integrated circuit, comprising:

a multi-bit flip-flop circuit with a first plurality of flip-flop circuits and a second plurality of flip-flop circuits, wherein the first plurality of flip-flop circuits are positioned in a first tier and the second plurality of flip-flop circuits are positioned in a second tier above the first tier;

a common clock circuit positioned in the first tier and connected to each of the first plurality of flip-flop circuits and each of the second plurality of flip-flop circuits;

a common scan circuit positioned in the second tier and connected to each of the first plurality of flip-flop circuits and each of the second plurality of flip-flop circuits;

wherein each of the first plurality of flip-flop circuits and each of the second plurality of flip-flop circuits comprises a clocked portion and a non-clocked portion;

wherein each clocked portion comprises a master latch component, a slave latch component, and a plurality of transmission gates; and

wherein each non-clocked portion comprises a data input, an inverted data input, a scan input, and a plurality of input/output transistors.

11. The integrated circuit of claim 10 , wherein the multi-bit flip-flop circuit is a four bit flip-flop circuit, the first plurality of flip-flop circuits comprises a second single bit flip-flop circuit and a fourth single bit flip-flop circuit, and the second plurality of flip-flop circuits comprises a first single bit flip-flop circuit and a third single bit flip-flop circuit.

12. The integrated circuit of claim 11 , wherein the first single bit flip-flop circuit is directly coupled to the common clock circuit, the second single bit flip-flop circuit is coupled to the first single bit flip-flop circuit, the third single bit flip-flop circuit is coupled to the second single bit flip-flop circuit, and the fourth single bit flip-flop circuit is coupled to the third single bit flip-flop circuit and directly coupled to the common clock circuit.

13. The integrated circuit of claim 12 , wherein the first single bit flip-flop circuit and the fourth single bit flip-flop circuit are directly coupled to the common scan circuit.

14. The integrated circuit of claim 13 , wherein the first single bit flip-flop circuit has an inverted output directly coupled to the common scan circuit.

15. The integrated circuit of claim 14 , wherein an inverted input of the first single bit flip-flop circuit is directly coupled to an inverted output of the second single bit flip-flop circuit.

16. The integrated circuit of claim 15 , wherein an inverted input of the second single bit flip-flop circuit is directly coupled to an inverted output of the third single bit flip-flop circuit.

17. The integrated circuit of claim 16 , wherein an inverted input of the third single bit flip-flop circuit is directly coupled to an inverted output of the fourth single bit flip-flop circuit.

18. The integrated circuit of claim 17 , further comprising routing pathways coupling the first tier to the second tier.