Phase lock loop circuit having a wide bandwidth
A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal.
1. A phase lock loop circuit comprising:
a phase detector having a first input that receives a reference signal with a predetermined waveform at a first frequency and a second input that receives a feedback signal, the phase detector being configured to generate a control signal with reference to the reference signal and the feedback signal;
a loop filter having an input that receives the control signal from an output of the phase detector, the loop filter being configured to generate a filtered control signal;
a voltage controlled oscillator (VCO) having an input that receives the filtered control signal from the loop filter, the VCO being configured to generate an output signal having a second frequency that corresponds to a multiple of the first frequency of the reference signal;
an analog to digital converter operatively connected to the first input of the phase detector to convert the reference signal to a digital reference signal for input to the phase detector; and
a digital to analog converter operatively connected to the output of the loop filter to convert a digital filtered control signal from the loop filter to an analog filtered control signal for the input of the VCO; and
a divider having an input that receives the output signal from the VCO, the divider further comprising:
a memory configured to store a lookup table of a plurality of discrete values corresponding to a sinusoidal feedback waveform; and
a controller operatively connected to the memory, the input of the divider, and an output of the divider, the controller being configured to:
detect a plurality of clock edges in the output signal from the VCO;
select one of the plurality of discrete values corresponding to the sinusoidal feedback waveform stored in the memory in response to each detected clock edge, the discrete values being selected in a predetermined order corresponding to the output signal from the VCO received at the input of the divider; and
generate the feedback signal for the second input of the phase detector as a sinusoidal waveform with reference to each selected discrete value in the plurality of discrete values corresponding to the sinusoidal feedback waveform stored in the memory.
2. The phase lock loop circuit of claim 1 , the loop filter further comprising:
a notch filter configured to attenuate an output of the phase detector around a frequency corresponding to twice the first frequency of the reference signal.
3. The phase lock loop circuit of claim 2 , the loop filter further comprising:
an zero-pole-integrator having an input operatively connected to an output of the notch filter.
4. The phase lock loop circuit of claim 1 wherein the VCO generates the output signal with a square waveform that includes the plurality of clock edges.