Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.
1. A silicon carbide semiconductor device comprising:
a silicon carbide layer having a first main surface and a second main surface opposite to the first main surface,
the silicon carbide layer including
a first region having n type conductivity, the first region defining the first main surface of the silicon carbide layer,
a second region provided in the first region, the second region having p type conductivity, and
a third region provided in the second region, the third region having the p type conductivity and having an impurity concentration higher than an impurity concentration of the second region;
a gate insulating film provided on the second region of the silicon carbide layer;
a gate electrode provided on the gate insulating film;
an interlayer insulating film provided to cover the gate insulating film and the gate electrode, the interlayer insulating film being provided with a first contact hole to expose the gate electrode; and
a gate pad provided on the interlayer insulating film, the gate pad being electrically connected to the gate electrode through the first contact hole,
the gate electrode including a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view,
the third region including
a central portion overlapping with the gate pad when viewed in the plan view, and
a first peripheral portion extending from the central portion toward the outside of the gate pad, the first peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.
2. The silicon carbide semiconductor device according to claim 1 , further comprising a gate runner provided to overlap with the second region when viewed in the plan view, the gate runner surrounding the gate electrode and being electrically connected to the gate pad, wherein
the gate electrode further includes a second comb-tooth shaped electrode portion extending from a side inwardly of the gate runner toward the gate runner and overlapping with the gate runner when viewed in the plan view,
the interlayer insulating film is provided with a second contact hole for electrically connecting the second comb-tooth shaped electrode portion of the gate electrode to the gate runner, and
the third region further includes a second peripheral portion extending toward an inner circumferential side of the gate runner, the second peripheral portion being provided to face the second comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.
3. The silicon carbide semiconductor device according to claim 1 , wherein the impurity concentration of the third region is not less than 5×1018 cm−3 and not more than 2×1020 cm−3.
4. The silicon carbide semiconductor device according to claim 1 , wherein the gate insulating film is a thermal oxidation film.
5. The silicon carbide semiconductor device according to claim 1 , further comprising:
a fourth region provided in the second region, the fourth region having the n type conductivity;
a fifth region provided in the second region, the fifth region having the p type conductivity;
an ohmic electrode in ohmic junction with the third region; and
a source pad electrically connected to the ohmic electrode, the fourth region, and the fifth region.