Selector for low voltage embedded memory
Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).
1. An integrated circuit comprising:
a first conductor;
a second conductor; and
a bitcell sandwiched between the first and second conductors and for storing a bit, the bitcell comprising a selector element serially connected with a memory element, wherein the selector element has a threshold voltage V TH , an ON-state voltage, and a snapback voltage V Snapback , the selector element configured to transition from an OFF-state to an ON-state in response to a voltage potential across the selector element exceeding V TH , and the selector element further configured to snap back to a hold voltage V H in response to transitioning to the ON-State, wherein V H is less than V TH and V Snapback is V TH −V H ;
wherein the memory element comprises a magnetic tunnel junction (MTJ) element.
2. The integrated circuit of claim 1 wherein the selector element is further configured to prevent the ON-state voltage from exceeding a maximum voltage potential across the first and second conductors, and wherein the maximum voltage potential applied across the first and second conductors is applied during a write to the bitcell.
3. A semiconductor device having the integrated circuit as defined in claim 2 , wherein the maximum voltage potential is less than 1 volt.
4. The device of claim 3 wherein the maximum voltage potential applied across the first and second conductors is applied during a write to the bitcell.
5. The device of claim 3 wherein the selector element comprises an insulator layer sandwiched between two electrodes, and the insulator layer comprises a crystalline material.
6. The device of claim 3 wherein the memory element comprises an insulator layer sandwiched between two ferromagnetic layers, with one of the ferromagnetic layers having a fixed magnetization direction and the other ferromagnetic layer having a changeable magnetization direction.
7. The device of claim 6 wherein the memory element further comprises a non-magnetic spacer layer sandwiched between one of the ferromagnetic layers and an offset layer, and the offset layer has a magnetization direction that is opposite fixed magnetization direction.
8. The device of claim 3 wherein the selector element is configured to transition from the ON-state to the OFF-state when the voltage potential across the selector element drops below V H .
9. The integrated circuit of claim 1 wherein the maximum voltage potential that can be applied across the first and second conductors is less than 1 volt.
10. The integrated circuit of claim 1 wherein the first conductor is a wordline and the second conductor is a bitline.
11. The integrated circuit of claim 1 wherein the selector element comprises an insulator layer sandwiched between two electrodes.
12. The integrated circuit of claim 11 wherein the insulator layer comprises a crystalline material.
13. The integrated circuit of claim 1 wherein the memory element comprises an insulator layer sandwiched between two electrodes.
14. The integrated circuit of claim 1 wherein the MTJ element comprises an insulator layer sandwiched between two ferromagnetic layers, with one of the ferromagnetic layers having a fixed magnetization direction and the other ferromagnetic layer having a changeable magnetization direction.
15. The integrated circuit of claim 14 wherein the MTJ element further comprises a non-magnetic spacer layer sandwiched between one of the ferromagnetic layers and an offset layer, and the offset layer has a magnetization direction that is opposite fixed magnetization direction.
16. The integrated circuit of claim 1 wherein the selector element is configured to transition from the ON-state to the OFF-state when the voltage potential across the selector element drops below V H .
17. A semiconductor device having the integrated circuit as defined in claim 1 .
18. An electronic system comprising the integrated circuit as defined in claim 1 .
19. The integrated circuit of claim 1 wherein the crystalline material comprises at least one of: VO 2 ; MnO; Ti 2 O 3 ; Fe 2 O 3 ; NbO 2 ; TaO 2 ; a perovskite structure having the chemical formula R (1-x) A x BO 3 , where R is a rare-earth atom, A is a bivalent atom, B is selected from manganese, nickel, cobalt, titanium, or vanadium; CrS; and FeS.
20. A method for fabricating a semiconductor device, the method comprising:
providing a first conductor;
providing a second conductor; and
providing a bitcell sandwiched between the first and second conductors and for storing a bit, the bitcell comprising a selector element serially connected with a memory element, wherein the selector element has a threshold voltage V TH , an ON-state voltage, and a snapback voltage V Snapback , the selector element configured to transition from an OFF-state to an ON-state in response to a voltage potential across the selector element exceeding V TH , and the selector element further configured to snap back to a hold voltage V H in response to transitioning to the ON-State, wherein V H is less than V TH and V Snapback is V TH −V H ;
wherein the memory element comprises a magnetic tunnel junction (MTJ) element.
21. An integrated circuit comprising:
a first conductor;
a second conductor; and
a bitcell sandwiched between the first and second conductors and for storing a bit, the bitcell comprising a selector element serially connected with a memory element;
wherein the selector element comprises an insulator layer sandwiched between two electrodes, and the insulator layer comprises a crystalline material,
wherein the selector element has a threshold voltage V TH and an ON-state voltage, and the crystalline material exhibits an S-shaped IV curve with snapback, the selector element configured to transition from an OFF-state to an ON-state in response to a voltage potential across the selector element exceeding V TH , and the selector element further configured to snap back to a hold voltage V H in response to transitioning to the ON-State, wherein V H is less than V TH and V Snapback is V TH −V H ; and
wherein the crystalline material comprises at least one of: VO 2 ; MnO; Ti 2 O 3 ; Fe 2 O 3 ; NbO 2 ; TaO 2 ; a perovskite structure having the chemical formula R (1-x) A x BO 3 , where R is a rare-earth atom, A is a bivalent atom, B is selected from manganese, nickel, cobalt, titanium, or vanadium; CrS, and FeS.