Semiconductor device with field threshold MOSFET for high voltage termination
View Patent ↗This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
1. A semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on top of a heavily doped layer and having an active cell area and an edge termination area wherein:
said edge termination area comprises a plurality of termination trenches formed in said lightly doped layer and lined with a dielectric layer and filled with a conductive material therein; and
a plurality of series connected MOSFET transistors, each of which comprises a trench gate region, a drain and source regions disposed on two opposite sides of each of said termination trenches, with said conductive material in each of said termination trenches functions as a trench gate for each of said MOSFET transistors, wherein each trench gate is electrically connected to said drain region.
2. The semiconductor power device of claim 1 wherein:
said plurality of MOSFET transistors comprising a plurality of P-channel MOSFET transistors.
3. The semiconductor power device of claim 1 wherein:
one of the plurality of MOSFET transistors is turned on when the applied voltage is greater than or equal to a threshold voltage of said MOSFET transistor, wherein said threshold voltage ranging from 0.5 to 80 volts.
4. The semiconductor power device of claim 1 wherein:
said edge termination has a width ranging from 5 microns to 250 microns to form between 1 to 25 termination trenches in said edge termination.
5. The semiconductor power device of claim 1 wherein:
said plurality of termination trenches are formed to have a distance ranging from 0.5 to 5 microns between two adjacent termination trenches.
6. The semiconductor power device of claim 1 wherein:
said plurality of termination trenches are formed to have a depth opened into said semiconductor substrate ranging from 0.5 to 8 microns.
7. The semiconductor power device of claim 1 wherein:
said drain and source regions disposed on two opposite sides of each of said termination trenches having a dopant concentration ranging from 1e17 cm −3 to 1e20 cm −3 .
8. The semiconductor power device of claim 1 wherein:
said threshold voltage of each MOSFET transistor is adjusted by localized variation of trench dielectric thickness and/or localized variation of doping concentration of said lightly doped layer of semiconductor substrate.
9. The semiconductor power device of claim 1 further comprising:
a first field plate starting from a vicinity of a last floating guard ring and expanding towards scribe lines:
a heavily doped channel stop region; and
a second field plate formed adjacent to said channel stop region and expanding towards said active cell area.
10. The semiconductor power device of claim 1 further comprising:
a first field plate starting from a vicinity of a last floating guard ring expanding towards scribe lines;
a heavily doped channel stop region with the same conductivity type as said lightly doped layer.
11. The semiconductor power device of claim 10 further comprising:
a second field plate formed adjacent to said channel stop region and expanding toward said active cell area.
12. The semiconductor power device of claim 1 wherein:
said heavily doped layer has opposite polarity compare to lightly doped layer to form an IGBTs.
13. The semiconductor power device of claim 1 wherein:
said heavily doped layer has the same polarity compare to lightly doped layer to form MOSFETs.