FET device having a vertical channel in a 2D material layer

1. A semiconductor device comprising:

a substrate;

a source/drain electrode stack over the substrate, wherein the source/drain electrode stack comprises a first source/drain electrode, a second source/drain electrode, and a dielectric layer interposed between the first source/drain electrode and the second source/drain electrode;

a source/channel/drain layer disposed on a first sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material, wherein a top surface of the source/channel/drain layer faces away from the substrate, wherein a portion of the top surface of the source/channel/drain layer extends below a top surface of the first source/drain electrode and away from the first sidewall of the source/drain electrode stack, and wherein the portion of the top surface of the source/channel/drain layer is parallel to a major surface of the substrate; and

a gate stack over the source/channel/drain layer.

2. The semiconductor device of claim 1 , wherein the 2D material is a transition metal dichalcogenide, graphene, or boron nitride.

3. The semiconductor device of claim 1 , wherein the source/channel/drain layer is disposed on a second sidewall of the source/drain electrode stack, the second sidewall of the source/drain electrode stack being opposite the first sidewall of the source/drain electrode stack.

4. The semiconductor device of claim 1 , wherein a first source/drain region of the source/channel/drain layer is disposed on a sidewall of the first source/drain electrode, and wherein a second source/drain region of the source/channel/drain layer is disposed on a sidewall of the second source/drain electrode.

5. The semiconductor device of claim 4 , wherein the first source/drain region comprises a first Schottky barrier, and wherein the second source/drain region comprises a second Schottky barrier.

6. The semiconductor device of claim 1 , wherein a width of the first source/drain electrode is larger than a width of the second source/drain electrode.

7. The semiconductor device of claim 1 , wherein a channel region of the source/channel/drain layer is disposed on a sidewall of the dielectric layer.

8. The semiconductor device of claim 7 , wherein a length of the channel region is substantially equal to a thickness of the dielectric layer.

9. A semiconductor device comprising:

a first conductive layer over a substrate, the first conductive layer having a first sidewall;

a first dielectric layer over the first conductive layer, the first dielectric layer having a second sidewall;

a second conductive layer over the first dielectric layer, the second conductive layer having a third sidewall, wherein the first sidewall and the second sidewall are substantially coplanar with the third sidewall;

a 2D material layer disposed on the first sidewall, the second sidewall, and the third sidewall, a portion of the 2D material layer extending horizontally over the substrate and away from the first sidewall, the portion of the 2D material layer extending below a top surface of the first conductive layer;

a second dielectric layer over the 2D material layer;

a third conductive layer over the second dielectric layer;

a first conductive plug in electrical contact with the first conductive layer;

a second conductive plug in electrical contact with the second conductive layer; and

a third conductive plug in electrical contact with the third conductive layer.

10. The semiconductor device of claim 9 , wherein the 2D material layer, the second dielectric layer, and the third conductive layer have a same width.

11. The semiconductor device of claim 9 , wherein the first conductive layer, the second conductive layer, and the first dielectric layer have a same width.

12. The semiconductor device of claim 9 , wherein the first conductive plug extends through the second conductive layer and the first dielectric layer.

13. The semiconductor device of claim 12 , wherein the first conductive plug is electrically isolated from the second conductive layer by a third dielectric layer disposed on sidewalls of the first conductive plug.

14. The semiconductor device of claim 9 , wherein the first conductive plug extends through the first dielectric layer.

15. A method of forming a semiconductor device, the method comprising:

forming a first dielectric layer over a substrate;

forming a source/drain electrode stack over the first dielectric layer, wherein the source/drain electrode stack comprises a first source/drain electrode, a second dielectric layer over the first source/drain electrode, and a second source/drain electrode over the second dielectric layer;

forming a source/channel/drain layer on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material, wherein at least a portion of the source/channel/drain layer extends along and contacts a topmost surface of the first dielectric layer, and wherein the topmost surface of the first dielectric layer is a farthest surface of the first dielectric layer from the substrate; and

forming a gate stack on the source/channel/drain layer, wherein at least a portion of the gate stack physically contacts the topmost surface of the first dielectric layer.

16. The method of claim 15 , wherein a width of the source/channel/drain layer substantially equals to a width of the gate stack.

17. The method of claim 15 , further comprising:

forming an interlayer dielectric layer over the gate stack;

forming a first conductive plug through the interlayer dielectric layer, the second source/drain electrode, and the second dielectric layer, the first conductive plug being in electrical contact with the first source/drain electrode;

forming a second conductive plug through the interlayer dielectric layer, the second conductive plug being in electrical contact with the second source/drain electrode; and

forming a third conductive plug through the interlayer dielectric layer, the third conductive plug being in electrical contact with the gate stack.

18. The method of claim 15 , further comprising:

forming an interlayer dielectric layer over the gate stack;

forming a first conductive plug through the interlayer dielectric layer and the second dielectric layer, the first conductive plug being in electrical contact with the first source/drain electrode;

forming a second conductive plug through the interlayer dielectric layer, the second conductive plug being in electrical contact with the second source/drain electrode; and

forming a third conductive plug through the interlayer dielectric layer, the third conductive plug being in electrical contact with the gate stack.

19. The method of claim 18 , wherein the first conductive plug is laterally spaced apart from the second source/drain electrode.

20. The semiconductor device of claim 1 , wherein the first source/drain electrode comprises a first material and the second source/drain electrode comprises a second material, the first material being different from the second material.