EEPROM core structure embedded into BCD process and forming method thereof

1. An EEPROM core structure embedded into a BCD process, comprising a selection transistor and a storage transistor connected in series, characterized in that, the selection transistor is an LDNMOS transistor, wherein a tunneling dielectric layer of the storage transistor and gate dielectrics of the LDNMOS transistor form in the same technology step, a floating gate of the storage transistor and a gate of LDNMOS transistor form in the same technology step, and a source region and a drain region of the storage transistor and a source region and a drain region of LDNMOS transistor form in the same technology step, and wherein the source region of the LDNMOS transistor abuts the drain region of the storage transistor.

2. The EEPROM core structure embedded into BCD process according to claim 1 , characterized in that, a floating gate of the storage transistor has a hollow box-shape plane figure, which includes a first side and a second side that extend along a first direction, a third side and a fourth side that extend along a second direction, wherein the first direction is parallel to an extending direction of an active area of the storage transistor, the second direction is perpendicular to the first direction, the active area of the storage transistor is located between the first side and the second side.

3. The EEPROM core structure embedded into BCD process according to claim 2 , characterized in that, the third side is close to the drain region of the storage transistor, the fourth side is close to the source region of the storage transistor, a tunnel injection layer of the storage transistor is located in the active area of the storage transistor under the third side.

4. The EEPROM core structure embedded into BCD process according to claim 3 , characterized in that, a tunneling dielectric layer of he storage transistor is located under the third side and located above the tunnel injection layer, under the fourth side there is an isolating dielectric layer having a thickness identical to that of the gate dielectric layer of the selection transistor and greater than that of the tunneling dielectric layer.

5. A method for forming an EEPROM core structure embedded into BCD process, characterized in comprising:

providing a semiconductor substrate, forming an N-well, active areas and a P-well in the semiconductor substrate, wherein the active areas include an active area of a selection transistor located in the N-well and an active area of a storage transistor located in the P-well;

performing tunnel ion implanting on the active area of the storage transistor, forming a tunnel injection layer in the active area of the storage transistor;

forming a gate dielectric layer for the selection transistor on the active area of the selection transistor, forming a tunneling dielectric layer for the storage transistor on the tunnel injection layer;

forming a gate of the selection transistor on the gate dielectric layer of the selection transistor, forming a floating gate of the storage transistor on the tunneling dielectric layer;

forming a floating gate dielectric layer and a control gate in sequence on the floating gate of the storage transistor, wherein the floating gate is covered by the floating gate dielectric layer, and the floating gate dielectric layer is covered by the control gate;

forming a source region and a drain region of the selection transistor in the active area of the selection transistor at two sides of the gate of the selection transistor, forming a source region and a drain region of the storage transistor in the active area of the storage transistor at two sides of the control gate, wherein the selection transistor is an LDNMOS transistor.

6. The method for forming an EEPROM core structure embedded into BCD process according to claim 5 , characterized in that, forming a gate of the selection transistor on the gate dielectric layer of the selection transistor and forming a floating gate of the storage transistor on the tunneling dielectric layer comprise: forming a first polysilicon layer and etching the first polysilicon layer to form the gate of the selection transistor and the floating gate, wherein the floating gate has a hollow box-shaped plane figure, which includes a first side and a second side that extend along a first direction, a third side and a fourth side that extend along a second direction, wherein the first direction is parallel to an extending direction of the active area of the storage transistor, the second direction is perpendicular to the first direction, the active area of the storage transistor is located between the first side and the second side.

7. The method for forming an EEPROM core structure embedded into BCD process according to claim 6 , characterized in that, the source region of the selection transistor abuts the drain region of the storage transistor.

8. The method for forming an EEPROM core structure embedded into BCD process according to claim 7 , characterized in that, the third side is close to the drain region of the storage transistor, the fourth side is close to the source region of the storage transistor, and the third side covers the tunnel injection layer of the storage transistor.

9. The method for forming an EEPROM core structure embedded into BCD process according to claim 6 , characterized in that, an isolating dielectric layer is further formed on the active area of the storage transistor during the formation of the gate dielectric layer of the selection layer and the tunneling dielectric layer of the storage layer, the fourth side of the floating gate is formed on the isolating dielectric layer, and the isolating dielectric layer has a thickness identical to that of the gate dielectric layer of the selection transistor and greater than that of the tunneling dielectric layer.

10. The method for forming an EEPROM core structure embedded into BCD process according to claim 5 , characterized in that, the formation of the control gate comprises: forming a second polysilicon layer and etching the second polysilicon layer to form the control gate of the storage transistor, and forming a capacitor plate of a peripheral circuit.

11. The method for forming an EEPROM core structure embedded into BCD process according to claim 5 , characterized in that, after forming the source region of the selection transistor and the drain region of the storage transistor, the method further comprises:

forming metal silicide on the surface of the source regions and the drain regions of the selection transistor and the storage transistor;

forming an inter-layer dielectric layer covering the selection transistor and the storage transistor;

forming contact holes in the inter-layer dielectric layer above the source regions and the drain regions of the selection transistor and the storage transistor, the gate of the selection transistor and/or the control gate of the storage transistor;

filling interconnection structures in the contact holes.