IP Library › Granted Patent US 9,557,922
Granted Patent B2
US 9,557,922 · App. 15/086,782 · Granted Jan 31, 2017

System and method for peer-to-peer PCIe storage transfers

Inventors: Colin Christopher McCambridge (Rochester, MN); Christopher William Barr (Rochester, MN); Adam Christopher Geml (Rochester, MN)
Assignee: HGST Netherlands B.V.
G06F3/0613G06F3/061G06F3/0659G06F3/0679G06F3/0688G06F13/4022G06F13/4278G06F13/4282G06F2206/1014
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Quick Facts
Patent No.
US 9,557,922
App. No.
15/086,782
Granted
Jan 31, 2017
Kind
B2
Abstract

Techniques for peer-to-peer Peripheral Component Interconnect Express (PCIe) storage transfers are disclosed. In some embodiments, the techniques may be realized as a method for providing peer-to-peer storage transfers between PCIe devices including providing, in memory of a first PCIe device, a queue for data communicated between the first PCIe device and a target PCIe device, receiving, at the first PCIe device, queue memory allocation information transmitted from a host device communicatively coupled to the first PCIe device and the target PCIe device, and generating, using a computer processor of the first PCIe device, a storage command.

Claims (36)

1. A method for providing peer-to-peer storage transfers between Peripheral Component Interconnect Express (PCIe) devices comprising:

providing, in memory of a first PCIe device:

a queue for data communicated between the first PCIe device and a target PCIe device;

a data buffer comprising at least one of scatter-gather lists and Physical Region Pages for processing a command between the first PCIe device and the target PCIe device; and

a queue management module that contains instructions for processing a command, wherein the queue management module stores one or more memory locations provided by a host device, associated with at least one or more of queues, doorbells, interrupts and data buffers;

receiving, at the first PCIe device, queue memory allocation information transmitted from the host device communicatively coupled to the first PCIe device and the target PCIe device; and

generating, using a computer processor of the first PCIe device, a storage command.

2. The method of claim 1 , comprising transferring data between the first PCIe device and the target PCIe device using at least one of the scatter-gather lists and the Physical Region Pages.

3. The method of claim 1 , wherein the storage command comprises at least one of a block read and a block write.

4. The method of claim 1 , wherein the queue comprises an I/O (Input/Output) submission queue for communication of a storage command to the target PCIe device.

5. The method of claim 1 , wherein the queue comprises an I/O (Input/Output) completion queue for receiving an indication of storage command completion from the target PCIe device.

6. A computer program product tangibly embodied in a non-transitory computer-readable medium including instructions for providing peer-to-peer storage transfers between Peripheral Component Interconnect Express (PCIe) devices; the computer program product implementing the steps of:

providing, in memory of a first PCIe device:

a queue for data communicated between the first PCIe device and a target PCIe device;

a data buffer comprising at least one of scatter-gather lists and Physical Region Pages for processing a command between the first PCIe device and the target PCIe device; and

a queue management module that contains instructions for processing a command, wherein the queue management module stores one or more memory locations provided by a host, associated with at least one or more of queues, doorbells, interrupts and data buffers;

receiving, at the first PCIe device, queue memory allocation information transmitted from a host device communicatively coupled to the first PCIe device and the target PCIe device; and

generating, using a computer processor of the first PCIe device, a storage command.

7. The computer program product of claim 6 , wherein the computer program product implements the step of transferring data between the first PCIe device and the target PCIe device using at least one of the scatter-gather lists and the Physical Region Pages.

8. The computer program product of claim 6 , wherein the storage command comprises at least one of a block read and a block write.

9. The computer program product of claim 6 , wherein the queue comprises an I/O (Input/Output) submission queue for communication of a storage command to the target PCIe device.

10. The computer program product of claim 6 , wherein the queue comprises an I/O (Input/Output) completion queue for receiving an indication of storage command completion from the target PCIe device.

11. A system for providing peer-to-peer storage transfers between Peripheral Component Interconnect Express (PCIe) devices, the system comprising:

a host device;

a first Peripheral Component Interconnect Express (PCIe) device;

a target Peripheral Component Interconnect Express (PCIe) device; and

a Peripheral Component Interconnect Express (PCIe) switch communicatively coupling the first PCIe device, the target PCIe device and the host; and

wherein the first PCIe device comprises:

a data buffer stored in memory that includes at least one of scatter-gather lists and Physical Region Pages for processing a command between the first PCIe device and the target PCIe device;

a queue management module that contains instructions for processing a command, wherein the queue management module stores one or more memory locations provided by a host, associated with at least one or more of queues, doorbells, interrupts and data buffers; and

stored Non-Volatile Memory express (NVMe) command submission instructions stored in memory, the instructions comprising:

an address of a queue in memory of the first PCIe device for I/O submission; and

instructions for generating an NVMe command.

12. The system of claim 11 , wherein data is transferred between the first PCIe device and a target PCIe device using at least one of the scatter-gather lists and the Physical Region Pages.

13. The system of claim 11 , wherein the storage command comprises at least one of a block read and a block write.

14. The system of claim 11 , wherein the queue comprises an I/O (Input/Output) submission queue for communication of a storage command to the target PCIe device.

Assignments (7)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2016
From: MCCAMBRIDGE, COLIN CHRISTOPHER; BARR, CHRISTOPHER WILLIAM; GEML, ADAM CHRISTOPHER
To: HGST NETHERLANDS B.V.
Reel/Frame 038340/0836 →
Continuity (2)
Continuation 14272214 · May 7, 2014
Related Publication 20160210062A1 · Jul 21, 2016