IP Library › Granted Patent US 9,558,152
Granted Patent B2
US 9,558,152 · App. 14/026,469 · Granted Jan 31, 2017

Synchronization method, multi-core processor system, and synchronization system

Inventors: Koichiro Yamashita (Hachioji, JP); Hiromasa Yamauchi (Kawasaki, JP); Takahisa Suzuki (Kawasaki, JP); Koji Kurihara (Kawasaki, JP)
Assignee: FUJITSU LIMITED
G06F15/7839G06F9/30087G06F9/3842G06F9/52G06F9/544G06F8/458G06F9/3834G06F9/3838G06F9/3885G06F9/467G06F15/167G06F2212/507
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Quick Facts
Patent No.
US 9,558,152
App. No.
14/026,469
Granted
Jan 31, 2017
Kind
B2
Abstract

A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.

Claims (34)

1. A synchronization method executed by a multi-processor system, the synchronization method comprising:

sending, by a first CPU among a plurality of CPUs, a synchronous signal that is issued based on a synchronous command included in a synchronization processing to the plurality of CPUs excluding the first CPU, the plurality of CPUs accessing a first shared memory area to execute the synchronization processing;

increasing, by a second CPU among the plurality of CPUs and different from the first CPU and based on receiving the synchronous signal from the first CPU, an arrival count for a synchronous point by one, the synchronous point indicating a position of the synchronous command in the synchronization processing and the arrival count indicating a number of CPUs arriving at the synchronous point among the plurality of CPUs;

sending, by the second CPU, a ready signal indicating an arrival to the synchronous point, to the plurality of CPUs excluding the first CPU and the second CPU as a result of increasing the arrival count by one;

creating, by the second CPU, a second shared memory area and a third shared memory area that are a duplication of the first shared memory area and accessing, by the second CPU, data stored only in the second shared memory area to execute a subsequent processing subsequent to the synchronization processing when the arrival count is not equal to count of the CPUs excluding the first CPU as a result of increasing the arrival count by one;

when the arrival count is equal to the count of the CPUs excluding the first CPU as a result of receiving the ready signal from a CPU different from the second CPU and the first CPU:

first comparing, by the second CPU, the second shared memory area and the third shared memory area,

when a first comparing result indicates a coincidence, second comparing, by the second CPU, the first shared memory area and the second shared memory area,

when a second comparing result indicates a coincidence, the CPUs excluding the first CPU are synchronized and the synchronization processing is complete,

when the first comparing result or the second comparing result indicates a non-coincidence, interrupting and re-executing the subsequent processing.

2. A multi-processor system comprising:

a first CPU, among a plurality of CPUs, that is configured to send a synchronous signal that is issued based on a synchronous command included in a synchronization processing to the plurality of CPUs excluding the first CPU, the plurality of CPUs accessing a first shared memory area to execute the synchronization processing; and

a second CPU among the plurality of CPUs that is different from the first CPU and is configured to:

increase, based on receiving the synchronous signal from the first CPU, an arrival count for a synchronous point by one, the synchronous point indicating a position of the synchronous command in the synchronization processing and the arrival count indicating a number of CPUs arriving at the synchronous point among the plurality of CPUs;

send a ready signal indicating an arrival to the synchronous point to the plurality of CPUs excluding the first CPU and the second CPU as a result of increasing the arrival count by one;

create a second shared memory area and a third shared memory area by duplicating the first shared memory area and access data stored only in the second shared memory area to execute a subsequent processing subsequent to the synchronization processing when the arrival count is not equal to count of the CPUs excluding the first CPU as a result of increasing the arrival count by one;

when the arrival count is equal to the count of the CPUs excluding the first CPU as a result of receiving the ready signal from a CPU different from the second CPU and the first CPU:

first compare, by the second CPU, the second shared memory area and the third shared memory area,

when a first comparing result indicates a coincidence, second comparing, by the second CPU, the first shared memory area and the second shared memory area,

when a second comparing result indicates a coincidence, the CPUs excluding the first CPU are synchronized and the synchronization processing is complete,

when the first comparing result or the second comparing result indicates a non-coincidence, interrupting and re-executing the subsequent processing.

3. The multi-processor system according to claim 2 , wherein the second CPU is further configured to

deactivate reception of the synchronous signal when the first comparing result or the second comparing result indicates the non-coincidence.

4. A synchronization system comprising:

a plurality of CPUs including at least a first CPU, the first CPU accessing a first shared memory area to execute synchronization processing, the first CPU being configured to send a synchronous signal that is issued based on a synchronous command included in a synchronization processing to the plurality of CPUs excluding the first CPU; and

a second CPU among the plurality of CPUs and different from the first CPU configured to:

increase, based on receiving the synchronous signal from the first CPU, an arrival count for a synchronous point by one, the synchronous point indicating a position of the synchronous command in the synchronization processing and the arrival count indicating a number of CPUs arriving at the synchronous point among the plurality of CPUs,

send a ready signal indicating an arrival to the synchronous point to the plurality of CPUs excluding the first CPU and the second CPU as a result of increasing the arrival count by one,

create a second shared memory area and a third shared memory area by duplicating the first shared memory area and access data stored only in the second shared memory area to execute a subsequent processing subsequent to the synchronization processing when the arrival count is not equal to count of the CPUs excluding the first CPU as a result of increasing the arrival count by one,

when the arrival count is equal to the count of the CPUs excluding the first CPU as a result of receiving the ready signal from a CPU different from the second CPU and the first CPU:

first compare, by the second CPU, the second shared memory area and the third shared memory area,

when a first comparing result indicates a coincidence, second compare, by the second CPU, the first shared memory area and the second shared memory area,

when a second comparing result indicates a coincidence, the CPUs excluding the first CPU are synchronized and the synchronization processing is complete,

when the first comparing result or the second comparing result indicates a non-coincidence, interrupt and re-execute the subsequent processing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2016
From: YAMASHITA, KOICHIRO; YAMAUCHI, HIROMASA; SUZUKI, TAKAHISA; KURIHARA, KOJI
To: FUJITSU LIMITED
Reel/Frame 040398/0870 →
Continuity (2)
Continuation PCTJP2011056262 · Mar 16, 2011
Related Publication 20140019717A1 · Jan 16, 2014