Method for regulating reading voltage of NAND flash memory device
A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.
1. A method of adjusting read voltages for a NAND flash memory device, the method comprising:
reading first page data from a first page corresponding to a paired page of a second page;
dividing a range of a first test read voltage and a range of a third test read voltage into a plurality of sections;
simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page;
performing a bitwise operation on the first page data and the second page data;
counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation; and
setting a first read voltage as a voltage corresponding to a section in which a change in the number of memory cells corresponding to the first threshold voltage state is a lowest value in the range of the first test read voltage, and setting a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells corresponding to the fourth threshold voltage state is a lowest value in the range of the third test read voltage.
2. The method of claim 1 , wherein each of the memory cells is a multi-level cell (MLC).
3. The method of claim 2 , wherein the first page is a least significant bit (LSB) page, and
wherein the second page is a most significant bit (MSB) page.
4. The method of claim 1 , wherein the change in the number of memory cells is calculated based on a 1 bit count of the result of the bitwise operation.
5. The method of claim 1 , wherein the bitwise operation is performed according to [Logic Equation 1] below:
THV1=PD1 AND PD2, [Logic Equation 1]
wherein THV 1 is a value of the first threshold voltage state, PD 1 is the first page data, and PD 2 is the second page data.
6. The method of claim 1 , wherein the bitwise operation is performed according to [Logic Equation 2] below:
THV4=(PD1 XOR PD2) AND PD2, [Logic Equation 2]
wherein THV 4 is a value of the fourth threshold voltage state, PD 1 is the first page data, and PD 2 is the second page data.
7. The method of claim 1 , wherein the first read voltage or the third read voltage is set as a median value of the section in which the change in the number of memory cells is a lowest value.
8. The method of claim 1 , wherein the section in which the change in the number of memory cells corresponding to the first threshold voltage state or the fourth threshold voltage state is a lowest value is searched using a binary search manner.