Semiconductor device and integrated circuit
A semiconductor device includes a first semiconductor region that has an external profile including at least one corner, and that includes a semiconductor of a first conductivity type, and a first insulation region that surrounds an outer periphery of the first semiconductor region, and that includes an insulator that, at a corner portion corresponding to the corner, has a depth deeper than a depth at a location other than the corner portion. The semiconductor device further includes a second semiconductor region that surrounds an outer periphery of the first insulation region, and that includes a semiconductor of a second conductivity type, and a second insulation region that surrounds an outer periphery of the second semiconductor region, and that includes an insulator that is deeper than the depth of the first insulation region at the location other than the corner portion.
1. A semiconductor device comprising:
a first semiconductor region that has an external profile including at least one corner in a plan view, and that includes a semiconductor of a first conductivity type;
a first insulation region that surrounds an outer periphery of the first semiconductor region in a plan view, and that has a ring shape in a plan view;
a first insulator that is a part of the first insulation region, and that is located at a corner portion of the ring shape of the first insulation region in a plan view;
a second insulator that is a part of the first insulation region, that is located at a location other than the corner portion of the first insulation region in a plan view, and that has a depth shallower than a depth of the first insulator;
a second semiconductor region that surrounds an outer periphery of the first insulation region in a plan view, and that includes a semiconductor of a second conductivity type that is different from the first conductivity type;
a second insulation region that surrounds an outer periphery of the second semiconductor region; and
a third insulator that is a part of the second insulation region, and that has a depth deeper than the depth of the second insulator.
2. The semiconductor device of claim 1 , wherein:
a minimum length of a current path located between the first semiconductor region and the second semiconductor region and passing under the corner portion of the ring shape of the first insulation region is 1.5 times a minimum length or greater of a current path located between the first semiconductor region and the second semiconductor region and passing under a location of the first insulation region other than the corner portion of the ring shape of the first insulation region.
3. The semiconductor device of claim 1 , further comprising a plurality of contacts connected to the second semiconductor region, wherein:
the second semiconductor region has ring shape in a plan view; and
a contact density at a corner portion of the ring shape of the second semiconductor region is less than a contact density at a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
4. The semiconductor device of claim 3 , wherein:
the contact density at the corner portion of the ring shape of the second semiconductor region is equal to or less than 67% of the contact density at the location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
5. The semiconductor device of claim 1 , further comprising a plurality of contacts connected to the second semiconductor region, wherein:
the second semiconductor region has a ring shape in a plan view; and
a contact density at a corner portion of the ring shape of the second semiconductor region is the same as a contact density at a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
6. The semiconductor device of claim 1 , further comprising a plurality of contacts connected to the second semiconductor region, and wherein:
the second semiconductor region has a ring shape in a plan view;
no contact is connected to a corner portion of the ring shape of the second semiconductor region; and
the plurality of contacts are connected to a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
7. The semiconductor device of claim 1 , wherein:
the first semiconductor region has a rectangular shaped external profile in a plan view; and
the corner portion of the ring shape of the first insulation region is a portion of the first insulation region extending between respective extension lines of two mutually adjacent edges of an outline of the first semiconductor region in a plan view.
8. The semiconductor device of claim 7 , wherein:
the second semiconductor region has a ring shape in a plan view; and
a corner portion of the ring shape of the second semiconductor region is a portion of the second semiconductor region extending between respective extension lines of two mutually adjacent edges of an outline of the first semiconductor region in a plan view.
9. The semiconductor device of claim 1 , wherein:
the first semiconductor region includes an n-type semiconductor formed in a surface portion of a p-type well; and
the second semiconductor region includes a p-type semiconductor formed in the surface portion of the p-type well.
10. The semiconductor device of claim 1 , wherein:
the first semiconductor region includes a p-type semiconductor formed in a surface portion of an n-type well; and
the second semiconductor region includes an n-type semiconductor formed in the surface portion of the n-type well.
11. An integrated circuit comprising:
a first semiconductor region that has an external profile including at least one corner in a plan view, and that includes a semiconductor of a first conductivity type;
a first insulation region that surrounds an outer periphery of the first semiconductor region in a plan view, and that has a ring shape in a plan view;
a first insulator that is a part of the first insulation region, and that is located at a corner portion of the ring shape of the first insulation region in a plan view;
a second insulator that is a part of the first insulation region, that is located at a location other than the corner portion of the first insulation region in a plan view, and that has a depth shallower than a depth of the first insulator;
a second semiconductor region that surrounds an outer periphery of the first insulation region in a plan view, and that includes a semiconductor of a second conductivity type that is different from the first conductivity type;
a second insulation region that surrounds an outer periphery of the second semiconductor region;
a third insulator that is a part of the second insulation region, and that has a depth deeper than the depth of the second insulator; and
a circuit connected to the first semiconductor region and the second semiconductor region through different lines.
12. The integrated circuit of claim 11 , wherein:
a minimum length of a current path located between the first semiconductor region and the second semiconductor region and passing under the corner portion of the ring shape of the first insulation region is 1.5 times a minimum length or greater of a current path located between the first semiconductor region and the second semiconductor region and passing under a location of the first insulation region other than the corner portion of the ring shape of the first insulation region.
13. The integrated circuit of claim 11 , further comprising a plurality of contacts connected to the second semiconductor region, wherein:
the second semiconductor region has ring shape in a plan view; and
a contact density at a corner portion of the ring shape of the second semiconductor region is less than a contact density at a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
14. The integrated circuit of claim 13 , wherein:
the contact density at the corner portion of the ring shape of the second semiconductor region is equal to or less than 67% of the contact density at the location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
15. The integrated circuit of claim 11 , further comprising a plurality of contacts connected to the second semiconductor region, wherein:
the second semiconductor region has a ring shape in a plan view, and
a contact density at a corner portion of the ring shape of the second semiconductor region is the same as a contact density at a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
16. The integrated circuit of claim 11 , further comprising a plurality of contacts connected to the second semiconductor region, and wherein:
the second semiconductor region has a ring shape in a plan view;
no contact is connected to a corner portion of the ring shape of the second semiconductor region; and
the plurality of contacts are connected to a location of the second semiconductor region other than the corner portion of the ring shape of the second semiconductor region.
17. The integrated circuit of claim 11 , wherein:
the first semiconductor region has a rectangular shaped external profile in a plan view; and
the corner portion of the ring shape of the first insulation region is a portion of the first insulation region extending between respective extension lines of two mutually adjacent edges of an outline of the first semiconductor region in a plan view.
18. The integrated circuit of claim 17 , wherein:
the second semiconductor region has ring shape in a plan view; and
a corner portion of the ring shape of the second semiconductor region is a portion of the second semiconductor region extending between respective extension lines of two mutually adjacent edges of an outline of the first semiconductor region in a plan view.
19. The integrated circuit of claim 11 , wherein:
the first semiconductor region includes an n-type semiconductor formed in a surface portion of a p-type well; and
the second semiconductor region includes a p-type semiconductor formed in the surface portion of the well.
20. The integrated circuit of claim 11 , wherein:
the first semiconductor region includes a p-type semiconductor formed in a surface portion of an n-type well; and
the second semiconductor region includes an n-type semiconductor formed in the surface portion of the well.