Semiconductor memory with a multi-layer passivation layer formed over sidewalls of a variable resistance element

1. An electronic device comprising a semiconductor memory device that comprises:

a variable resistance element formed over a substrate; and

a multi-layer passivation layer positioned over sidewalls of the variable resistance element and having two or more insulating layers formed over the sidewalls of the variable resistance element,

wherein among the two or more insulating layers of the multi-layer passivation layer, a first insulating layer of the multi-layer passivation layer has a first impurity concentration higher than a second impurity concentration of a second insulating layer positioned closer than the first insulation layer to the variable resistance element.

2. The electronic device according to claim 1 , wherein the two or more insulating layers include a nitride.

3. The electronic device according to claim 1 , wherein each insulating layer includes a thin film formed through a deposition and a post-treatment.

4. The electronic device according to claim 1 , wherein the variable resistance element comprises a stacked layer of two magnetic layers and a tunnel barrier layer interposed therebetween.

5. The electronic device according to claim 1 , wherein the variable resistance element comprises a metal oxide.

6. The electronic device according to claim 1 , wherein the variable resistance element comprises a phase change material.

7. The electronic device according to claim 1 , wherein the two or more insulating layers comprise a silicon nitride.

8. The electronic device according to claim 1 , wherein:

the variable resistance element includes different layers that are formed over the substrate and are parallel to the substrate, and

the two or more insulating layers are perpendicular to the different layers of the variable resistance element.

9. The electronic device according to claim 8 , wherein the two or more insulating layers have a total thickness smaller than a total thickness of the different layers of the variable resistance element.

10. The electronic device according to claim 1 , wherein the semiconductor memory device further includes a reduction layer between each sidewall of the variable resistance element and the multi-layer passivation layer.

11. The electronic device according to claim 1 , further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data upon which the operation is performed,

wherein the semiconductor memory device that includes the variable resistance element is a part of the memory unit in the microprocessor.

12. The electronic device according to claim 1 , further comprising a processor which includes:

a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command;

a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data upon which the operation is performed; and

a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,

wherein the semiconductor memory device that includes the variable resistance element is a part of the cache memory unit in the processor.

13. The electronic device according to claim 1 , further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device, the main memory device and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the auxiliary memory device or the main memory device in the processing system.

14. The electronic device according to claim 1 , further comprising a data storage system which includes:

a storage device configured to store data and maintain stored data regardless of a power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller, and the temporary storage device and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the storage device or the temporary storage device in the data storage system.

15. The electronic device according to claim 1 , further comprising a memory system which includes:

a memory configured to store data and maintain stored data regardless of a power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller, and the buffer memory and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the memory or the buffer memory in the memory system.