IP Library › Granted Patent US 9,564,352
Granted Patent B2
US 9,564,352 · App. 14/626,567 · Granted Feb 7, 2017

Method for fabricating semiconductor device including isolation layer

Inventors: Jae-Soo Kim (Gyeonggi-do, KR); Hyung-Kyun Kim (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L21/76224H01L21/0223H01L21/02271H01L21/02282H01L21/76229H01L27/10844H01L27/10894H01L29/0649H01L27/10876
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Quick Facts
Patent No.
US 9,564,352
App. No.
14/626,567
Filed
Feb 19, 2015
Granted
Feb 7, 2017
Kind
B2
Art Unit
2814
USPC
257/513
Abstract

A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.

Claims (24)

1. A method for fabricating an isolation layer, comprising:

forming a trench in a substrate;

forming a first oxide layer in the trench; and

forming a second oxide layer by oxidizing the first oxide layer; and

forming a third oxide layer by oxidizing the substrate adjacent to the trench when the second oxide layer is formed.

2. The method of claim 1 , further comprising forming a nitride layer to gap-fill the trench over the second oxide layer.

3. The method of claim 1 , wherein a region includes first and second trenches,

wherein the first trench has a first critical dimension (CD) and the second trench has a second critical dimension (CD), and

wherein the second CD is larger than the first CD.

4. The method of claim 3 , wherein the second oxide layer gap-fills the first CD and lines the second CD.

5. The method of claim 4 , further comprising gap-filling the second CD over the second oxide layer with a nitride layer.

6. The method of claim 2 , wherein the first oxide layer and the nitride layer are formed by chemical vapor deposition (CVD), and the second and third oxide layers are formed by a dry oxidation process.

7. The method of claim 1 , wherein the isolation layer isolates a plurality of active regions formed in a cell region of a memory device.

8. A method for fabricating an isolation layer, comprising:

forming a first trench having a first critical dimension (CD) and a third trench having a third critical dimension (CD) in a first region of a substrate;

forming a second trench having a second critical dimension in a second region of the substrate;

forming a first oxide layer in the first, the second, and the third trenches;

oxidizing the first oxide layer to form a second oxide layer, the second oxide layer gap-filling the first trench and lining the third trench and the second trench;

forming a nitride layer over the second oxide layer to gap fill the third trench and line the second trench;

forming a third oxide layer over the nitride layer to gap-fill the second trench; and

oxidizing the substrate located under the first oxide layer to form a fourth oxide layer under the first oxide layer and in a liner shape,

wherein the second oxide layer and the fourth oxide layer are formed substantially at the same time.

9. The method of claim 8 , wherein the first oxide layer and the nitride layer are formed by CVD, the second and fourth oxide layers are formed by a dry oxidation process, and the third oxide layer is formed by a spin coating method.

10. The method of claim 8 , wherein the isolation layer isolates a plurality of active regions formed in a cell region of a memory device.

Priority Claims (1)
KR 10-2012-0143247 · Dec 11, 2012 · national
Continuity (2)
Continuation 13828724 · Mar 14, 2013
Related Publication 20150162237A1 · Jun 11, 2015