Adaptive equalization using correlation of edge samples with data patterns
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
1. A double-data-rate (DDR) receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a first data sampler to sample the equalized data signal on edges of a first data-clock signal, thereby generating a first series of data samples;
a second data sampler to sample the equalized data signal on edges of a second data-clock signal, thereby generating a second series of data samples;
an edge sampler to sample at least one of the input data signal and the equalized data signal on edges of an edge-clock signal, thereby generating a series of edge samples; and
equalizer control circuitry to receive the first series of data samples, the second series of data samples, and the series of edge samples, the equalizer control circuitry including a phase detector to generate a relative-timing signal responsive to the first series of data samples and the series of edge samples, the equalizer control circuitry to adjust the equalizer responsive to the relative-timing signal and a specific pattern of the first and second series of data samples, the specific pattern including successive first bit values followed by a transition to a second bit value.
2. The DDR receiver of claim 1 , further comprising clock-recovery circuitry to recover the first and second data-clock signals responsive to the first and second series of data samples.
3. The DDR receiver of claim 1 , the equalizer control circuitry including memory to store the specific pattern.
4. The DDR receiver of claim 3 , the memory to store the specific pattern and at least one additional pattern, the equalizer control circuitry to adjust the equalizer responsive to the specific pattern and the at least one additional pattern.
5. The DDR receiver of claim 1 , the equalizer control circuitry further having a second edge sampler to sample at least one of the input data signal and the equalized data signal to produce a second series of edge samples, the phase detector to generate the relative-timing signal to phase adjust the first and second data-clock signals responsive to the first-mentioned and second series of edge samples.
6. The DDR receiver of claim 1 , further comprising a deserializer coupled to the first data sampler, the second data sampler, and the equalizer control circuitry, the deserializer to convey the first and second series of data samples to the equalizer control circuitry.
7. A double-data-rate (DDR) method of receiving an input data signal, the DDR method comprising:
equalizing the input data signal to create an equalized signal;
sampling the equalized signal on edges of a first clock signal to generate a first series of data samples, each data sample representing one of a first value and a second value;
sampling the equalized signal on edges of a second clock signal to generate a second series of data samples, each data sample representing one of the first value and the second value;
sampling at least one of the input data signal and the equalized signal on edges of a third clock signal to generate a series of edge samples;
comparing the first series of data samples with the series of edge samples to produce a relative-timing signal;
phase adjusting the first clock signal and the second clock signal responsive to the first and second series of data samples; and
adjusting the equalizing responsive to a specific pattern of the first and second series of data samples and the relative-timing signal, the specific pattern including successive bits of the first value followed by a transition to a bit of the second value.
8. The method of claim 7 , further comprising receiving and loading the specific pattern.
9. The method of claim 7 , further comprising adjusting the equalizing responsive to a second specific pattern of the first and second series of data samples.
10. The method of claim 7 , wherein the specific pattern includes a second transition to the first value exactly one bit after the transition to the bit of the second value.
11. A double-data-rate (DDR) receiver comprising:
an equalizer to issue an equalized data signal responsive to an input data signal;
a first data sampler to sample the equalized data signal on edges of a first data-clock signal, thereby generating a first series of data samples;
a second data sampler to sample the equalized data signal on edges of a second data-clock signal, thereby generating a second series of data samples;
an edge sampler to sample at least one of the input data signal and the equalized data signal on edges of an edge-clock signal, thereby generating a series of edge samples; and
equalizer control means for receiving the first series of data samples, the second series of data samples, and the series of edge samples, the equalizer control means including a phase detector to generate a relative-timing signal responsive to the first series of data samples and the series of edge samples, the equalizer control means to adjust the equalizer responsive to the relative-timing signal and a specific pattern of the first and second series of data samples, the specific pattern including successive first bit values followed by a transition to a second bit value.
12. The receiver of claim 11 , further comprising memory to load with the specific pattern.
13. The receiver of claim 12 , the memory to store the specific pattern and at least one additional pattern, the equalizer control means to adjust the equalizer responsive to the specific pattern and the at least one additional pattern.
14. The receiver of claim 11 , further comprising means for recovering complementary first and second clock signals from at least one of the input data signal and the equalized data signal, the first and second data samplers to sample the input data signal respectively timed to the first and second clock signals.