Programming dummy data into bad pages of a memory system and operating method thereof
A memory system includes a memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of pages each include a plurality of memory cells electrically coupled to a plurality of word lines and store write data and provide read data which are requested from a host, and a controller suitable for checking a bad page among a plurality of pages in a first memory block of the memory blocks, programming dummy data in the bad page, and process the first memory block as a normal block.
1. A memory system comprising:
a memory device including a plurality of memory blocks, each including a plurality of pages, wherein the plurality of pages each includes a plurality of memory cells electrically coupled to a plurality of word lines and store write data and provide read data which are requested from a host; and
a controller checking a bad page among a plurality of pages in a first memory block of the memory blocks, programming dummy data in the bad page, and processing the first memory block as a normal block,
wherein the controller determines a first page which is electrically coupled to the bad word line and a second page which is electrically coupled to a word line adjacent to the bad word line, among the plurality of pages in the first memory block, as bad pages,
wherein the plurality of word lines include the first to Lth word lines, wherein the bad word line corresponds to a Kth word line, the word lines adjacent to the bad word line correspond to the (K−1)th word line and the (K+1)th word line, and the (K−2)th word line and the (K+2)th word line are good word lines, where K is greater than or equal to 1 and is less than or equal to L.
2. The memory system according to claim 1 , wherein the controller determines a word line corresponding to the bad page among the plurality of word lines, as a bad word line.
3. The memory system according to claim 1 , wherein the controller checks a normal page which is available to be programmed with data, among the plurality of pages in the first memory block, and programs first data, which was to be programmed in the bad page of the first memory block, in the normal page of the first memory block.
4. The memory system according to claim 3 , wherein, after programming the first data in the normal page, the controller programs the dummy data in the bad page.
5. The memory system according to claim 1 , wherein the controller checks a normal page which is available to be programmed with data, among a plurality of pages included in a second memory block adjacent to the first memory block, and programs first data that was to be programmed in the bad page of the first memory block, in the normal page of the second memory block.
6. The memory system according to claim 5 , wherein, after programming the first data in the normal page, the controller programs the dummy data in the bad page.
7. The memory system according to claim 1 , wherein the controller processes the first memory block as a bad block, when the number of bad pages or the number of word lines corresponding to the bad pages exceeds a preset threshold.
8. A method for operating a memory system, comprising:
checking a bad page among a plurality of pages in each of a plurality of memory blocks of a memory device, wherein the plurality of pages each include a plurality of memory cells electrically coupled to a plurality of word lines;
checking a normal page which is available to be programmed with data, among a plurality of pages included in a first memory block among the memory blocks;
programming first data to be programmed in a bad page of the first memory block, in the normal page of the first memory block; and
programming dummy data in the bad page of the first memory block, and processing the first memory block as a normal block,
wherein the checking of the bad page includes: checking a first page which is electrically coupled to the bad word line and a second page which is electrically coupled to a word line adjacent to the bad word line, among the plurality of pages in each of the memory blocks, as bad pages,
wherein the plurality of word lines include the first to Lth word lines, wherein the bad word line corresponds to a Kth word line, the word lines adjacent to the bad word line correspond to the (K−1)th word line and the (K+1)th word line, and the (K−2)th word line and the (K+2)th word line are good word lines, where K is greater than or equal to 1 and is less than or equal to L.
9. The method according to claim 8 , wherein the checking of the bad page includes:
checking a word line corresponding to the bad page among the plurality of word lines, as a bad word line.
10. The method according to claim 8 , further comprising:
processing the first memory block as a bad block, when the number of bad pages or the number of word lines corresponding to the bad pages exceeds a preset threshold.
11. The method according to claim 8 , further comprising:
programming second data to be programmed in a bad page of a second memory block adjacent to the first memory block, in the normal page of the first memory block; and
programming the dummy data in the bad page of the second memory block, and processing the second memory block as the normal block.
12. A memory system comprising:
a memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of pages each includes a plurality of memory cells electrically coupled to a plurality of word lines; and
a controller checking a bad page among a plurality of pages in a first memory block of the memory blocks and determining whether the first memory block is a bad block based on a result of checking the bad page,
wherein the controller determines a word line corresponding to the bad page among the plurality of word lines, as a bad word line, and determines one or more pages which are electrically coupled to the bad word line and an adjacent word line of the bad word line, among the plurality of pages in the first memory block, as bad pages,
wherein the plurality of word lines include the first to Lth word lines, wherein the bad word line corresponds to a Kth word line, the word lines adjacent to the bad word line correspond to the (K−1)th word line and the (K+1)th word line, and the (K−2)th word line and the (K+2)th word line are good word lines, where K is greater than or equal to 1 and is less than or equal to L.
13. The memory system according to claim 12 , wherein, when the number of bad pages or the number of word lines corresponding to the bad pages is less than a preset threshold, the controller programs data to be programmed in the bad pages, in normal pages other than the bad pages among the plurality of pages in the first memory block, programs dummy data in the bad page, and processes the first memory block as a normal block.
14. The memory system according to claim 12 , wherein, when the number of bad pages or the number of word lines corresponding to the bad pages exceeds a preset threshold, the controller processes the first memory block as the bad block.
15. The memory system according to claim 13 , wherein, when the number of the normal pages is less than a preset number, the controller programs the data in normal pages of a second memory block adjacent to the first memory block.