Memory page buffer
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
1. A method of operating a memory having a page buffer circuit coupled to a plurality of bit lines, comprising:
using differential sense amplifiers to sense and store a first threshold state of memory cells coupled to the plurality of bit lines as previously sensed logic states; and
in preparation for an operation to sense a next threshold state of the memory cells coupled to the plurality of bit lines, charging bit lines in the plurality of bit lines selected based on the previously sensed logic state.
2. The method of claim 1 , further comprising:
performing drain side sensing on the plurality of bit lines.
3. The method of claim 1 , further comprising:
performing source side sensing on the plurality of bit lines.
4. The method of claim 1 ,
wherein the memory comprises a NAND memory, and control circuitry enables different ones of the plurality of differential sense amplifiers at different times, when reading multiple cells of the NAND memory at a time.
5. A method of operating a memory including multiple level cells, and having a page buffer circuit coupled to a plurality of bit lines, comprising:
first sensing threshold levels in multiple level cells coupled to the plurality of bit lines using a first gate voltage and storing the sensing result as first sensed data; and
charging bit lines in the plurality of bit lines selected based on the first sensed data, and then second sensing threshold levels in multiple level cells coupled to uncharged bit lines in the plurality of bit lines using a second gate voltage.
6. The method of claim 5 , including first programming the multiple level cells coupled to the plurality of bit lines and wherein the first sensing and second sensing are elements of a program verify operation.
7. The method of claim 5 , wherein the first gate voltage is lower than the second gate voltage.
8. The method of claim 5 , including using source side sensing for the first sensing and the second sensing.