High electron mobility transistor

1. A high electron mobility transistor (HEMT) comprising:

a channel layer that includes a first semiconductor material;

a channel supply layer that includes a second semiconductor material, the channel supply layer being configured to induce a two-dimensional electron gas (2DEG) in the channel layer;

a source electrode and a drain electrode that are at sides of the channel supply layer;

a depletion-forming layer that is disposed to protrude on the top surface of the channel supply layer, the depletion-forming layer being configured to form a depletion region in the 2DEG;

a gate insulating layer on the top surface of the depletion-forming layer; and

a gate electrode on the top surface of the gate insulating layer,

wherein the gate insulating layer defines an opening that exposes at least a portion of a top surface of the depletion-forming layer,

wherein the exposed top surface of the depletion-forming layer through the opening of the gate insulating layer directly contacts the source electrode,

wherein the gate electrode is insulated from the source electrode and the depletion-forming layer.

2. The HEMT of claim 1 , wherein the depletion-forming layer has a strip shape, and both side surfaces of the depletion-forming layer are inclined.

3. The HEMT of claim 1 , wherein the gate electrode includes first and second gate electrodes, the first and second gate electrodes are on the gate insulating layer, and

the first and second gate electrodes are on the both side surfaces of the depletion-forming layer.

4. The HEMT of claim 3 , wherein the first and second gate electrodes are on the both side surfaces of the depletion-forming layer in a longitudinal direction of the depletion-forming layer.

5. The HEMT of claim 3 , further comprising:

a passivation layer covering the first and second gate electrodes and the gate insulating layer, wherein

the passivation layer defines a via-hole that exposes the top surface of the depletion-forming layer, and

the source electrode contacts the top surface of the depletion-forming layer through the via-hole defined by the passivation layer.

6. The HEMT of claim 3 , wherein a top surface of the channel supply layer includes recesses on both sides of the depletion-forming layer, and the gate insulating layer extends to the recesses from the both sides of the depletion-forming layer.

7. The HEMT of claim 1 , wherein the opening defined by the gate insulating layer exposes an end portion of the depletion-forming layer, and the source electrode contacts the end portion of the depletion-forming layer through the opening in the gate insulating layer.

8. The HEMT of claim 7 , further comprising:

a passivation layer covering the gate electrode, the gate insulating layer, and the depletion-forming layer,

wherein the passivation layer defines a via-hole that exposes the end portion of the depletion-forming layer, and the source electrode is connected to the end portion of the depletion-forming layer through the via-hole defined by the passivation layer.

9. The HEMT of claim 1 , wherein the first semiconductor material is a GaN-based material.

10. The HEMT of claim 1 , wherein the second semiconductor material includes at least one nitride that includes at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B).

11. The HEMT of claim 1 , wherein the depletion-forming layer includes a p-type semiconductor material.

12. The HEMT of claim 11 , wherein the depletion-forming layer includes a group III-V nitride semiconductor material.

13. The HEMT of claim 1 , wherein a width of the depletion region in the 2DEG corresponds to a width of the depletion-forming layer.