Low-dropout voltage regulator

1. A low-dropout voltage regulator (LDO), comprising:

a power transistor, receiving a driving signal, controlled by the driving signal for switching and converting an input voltage into an output voltage to provide to a load;

a feedback circuit, coupled to the power transistor and generating a feedback voltage according to the output voltage;

a driving stage circuit, generating the driving signal according to the feedback voltage and the reference voltage;

a bias power source, coupled to the driving stage circuit and configured to provide a bias current; and

an auxiliary reference current generation circuit, coupled to the power transistor, the driving stage circuit and the bias power source and configured to sample an output current flowing through the power transistor, adjust the sampled output current to generate an adjustment current by means of mapping and superpose the adjustment current onto the bias current to generate a reference current to control drive capability of the driving stage circuit.

2. The LDO according to claim 1 , wherein the driving stage circuit comprises:

an error amplifier, having a first input terminal receiving the reference voltage and a second input terminal receiving the feedback voltage; and

an output buffer, having an input terminal coupled to an output terminal of the error amplifier and an output terminal coupled to the power transistor to provide the driving signal.

3. The LDO according to claim 2 , wherein the auxiliary reference current generation circuit comprises:

a sampling unit, coupled to the power transistor and configured to sample the output current, so as to generate a sampling current; and

a current mirror, coupled to the sampling unit, adjusting the sampling current as the adjustment current by means of mapping, superposing the adjustment current onto the bias current provided by the bias power source and generating the reference current to be provided to one of the error amplifier and the output buffer.

4. The LDO according to claim 3 , wherein the power transistor is an N-type transistor having a gate coupled to the output terminal of the output buffer, a drain receiving the input voltage and a source coupled to the load, and the sampling unit is a first N-type transistor having a gate coupled to the gate of the power transistor and a source coupled to the source of the power transistor.

5. The LDO according to claim 4 , wherein the current mirror comprises:

a first P-type transistor, having a gate and a drain jointly coupled to the drain of the first N-type transistor and a source receiving a positive power supply voltage; and

a second P-type transistor, having a gate coupled to the gate of the first P-type transistor, a drain coupled to an outflow end of the bias current of the bias power source and an inflow end of the reference current of the error amplifier and a source receiving the positive power supply voltage.

6. The LDO according to claim 5 , wherein the auxiliary reference current generation circuit further comprises:

a resistor, connected in serial between the drain of the first N-type transistor and the drain of the first P-type transistor.

7. The LDO according to claim 4 , wherein the current mirror comprises:

a first P-type transistor, having a gate and a drain jointly coupled to the drain of the first N-type transistor and a source receiving a positive power supply voltage; and

a second P-type transistor, having a gate coupled to the gate of the first P-type transistor, a drain coupled to an outflow end of the bias current of the bias power source and an inflow end of the reference current of the error amplifier and a source receiving the positive power supply voltage.

8. The LDO according to claim 7 , wherein the auxiliary reference current generation circuit further comprises:

a resistor, connected in serial between the drain of the first N-type transistor and the drain of the first P-type transistor.

9. The LDO according to claim 3 , wherein the power transistor is a P-type transistor having a gate coupled to the output terminal of the output buffer, a source receiving the input voltage and a drain coupled to the load, and the sampling unit is a first P-type transistor having a gate coupled to the gate of the power transistor and a source receiving the input voltage.

10. The LDO according to claim 9 , wherein the current mirror comprises:

a first N-type transistor, having a gate and a drain jointly coupled to the drain of the first P-type transistor and a source coupled to a negative power supply voltage; and

a second N-type transistor, having a gate coupled to the gate of the first N-type transistor, a drain coupled to an inflow end of the bias current of the bias power source and an outflow end of the reference current of the error amplifier and a source coupled to the negative power supply voltage.

11. The LDO according to claim 10 , wherein the auxiliary reference current generation circuit further comprises:

a resistor, connected in serial between the drain of the first P-type transistor and the drain of the first N-type transistor.

12. The LDO according to claim 9 , wherein the current mirror comprises:

a first N-type transistor, having a gate and a drain jointly coupled to the drain of the first P-type transistor and a source coupled to a negative power supply voltage; and

a second N-type transistor, having a gate coupled to the gate of the first N-type transistor, a drain coupled to an inflow end of the bias current of the bias power source and an outflow end of the reference current from the output buffer and a source coupled to the negative power supply voltage.

13. The LDO according to claim 12 , wherein the auxiliary reference current generation circuit further comprises:

a resistor, connected in serial between the drain of the first P-type transistor and the drain of the first N-type transistor.