Read-current and word line delay path tracking for sense amplifier enable timing

1. An integrated circuit comprising a solid-state memory, the solid-state memory comprising:

a memory array, comprising:

a sub-array of read/write memory cells arranged in rows and columns, each row of read/write memory cells coupled to an associated word line, and each column of read/write memory cells coupled to an associated pair of bit lines;

a plurality of word-line tracking memory cells disposed along a first side of the sub-array, each having a transistor gate coupled to a reference word line; and

a plurality of read-tracking memory cells disposed along a second side of the sub-array, each comprising a pass transistor having a conduction path between a reference storage node and the reference bit line, and having a gate;

a row decoder, for decoding a row address received by the solid-state memory;

a plurality of word line drivers, each for driving an associated selected word line responsive to the decoded row address and to a row enable signal;

a reference word line driver, connected to the reference word line, for driving the reference word line responsive to the row enable signal;

wherein the gates of the read-tracking memory cells are coupled to the reference word line at a point from the reference word line driver beyond locations at which the reference word line is coupled to the word-line tracking memory cells;

the memory further comprising:

a plurality of sense amplifiers, each coupled to a pair of bit lines; and

a plurality of enable transistors, each having a conduction path coupled between one of the plurality of sense amplifiers and a reference voltage, and having a gate coupled to the reference bit line.

2. The memory of claim 1 , wherein the plurality of read-tracking memory cells are arranged in a column along the second side of the sub-array; and wherein the plurality of word-line tracking memory cells are arranged in at least one row along the first side of the sub-array.

3. The memory of claim 2 , wherein the column of read-tracking memory cells is disposed adjacent to a column of read/write memory cells in the sub-array.

4. The memory of claim 2 , further comprising:

a first row of dummy memory cells disposed adjacent to a row of read/write memory cells in the sub-array; and

wherein the row of word-line tracking memory cells is disposed adjacent to the row of dummy memory cells.

5. The memory of claim 2 , further comprising:

a plurality of dummy memory cells comprising:

a first row of dummy memory cells disposed adjacent to a row of read/write memory cells in the sub-array, and between the row of read/write memory cells and the row of word-line tracking memory cells;

a second row of dummy memory cells disposed adjacent to and on an opposite side of a row of word-line tracking memory cells from the first row of dummy memory cells;

a first column of dummy memory cells disposed adjacent to a column of read/write memory cells, on an opposite side of the sub-array from the read-tracking memory cells; and

a second column of dummy memory cells disposed adjacent to the column of read-tracking memory cells.

6. The memory of claim 5 , wherein the column of read-tracking memory cells is disposed adjacent to a column of read/write memory cells in the sub-array.

7. The memory of claim 1 , wherein the plurality of word-line tracking memory cells are arranged in first and second rows; wherein the reference word line extends from the row driver over the first row of word-line tracking memory cells for a distance shorter than the length of the sub-array in that direction, and extends back in a direction toward the row driver over the second row of word-line tracking memory cells.

8. The memory of claim 1 , wherein the plurality of word-line tracking memory cells are arranged in a single row.

9. The memory of claim 1 , wherein each of the read/write memory cells is a static random-access memory cell.

10. The memory of claim 1 , further comprising:

a configuration register for storing a digital value indicating a number of read-tracking memory cells coupled to the reference word line.

11. The memory of claim 1 , further comprising:

a buffer having an input coupled to the reference bit line and an output coupled to the gate of each of the plurality of enable transistors.

12. A method of reading data from a solid-state memory array, the memory array comprising a sub-array of read/write memory cells arranged in rows and columns, comprising the steps of:

precharging a reference bit line;

decoding a row address portion of a memory address;

asserting a row enable signal;

responsive to the asserting step, driving a word line associated with a row of read/write memory cells corresponding to the decoded row address;

responsive to the asserting step, energizing a reference word line from a first end, the reference word line coupled to a plurality of word-line tracking memory cells disposed in the array near the sub-array, a second end of the reference word line disposed beyond the word-line tracking memory cells and coupled to a plurality of read-tracking memory cells disposed in the array near the sub-array;

responsive to receiving an active voltage level at the plurality of read-tracking memory cells, discharging the reference bit line; and

responsive to the discharging of the reference bit line, enabling at least one sense amplifier coupled to a pair of bit lines associated with a column of the read/write memory cells.

13. The method of claim 12 , wherein the enabling step comprises:

turning on an enable transistor having a conduction path coupled between an associated sense amplifier and a bias voltage.

14. The method of claim 12 , wherein the read/write memory cells in each column are associated with a pair of bit lines; and

wherein the read/write memory cells each comprise a pair of pass transistors, each having a conduction path coupled between a storage node and one of the pair of bit lines associated with its column, and having a gate coupled to the word line associated with its row;

and further comprising:

prior to the step of driving a word line, precharging each pair of bit lines.

15. The method of claim 14 , further comprising:

responsive to the driving step, turning on the pass transistors of each of the read/write memory cells in the row corresponding to the decoded row address; and

wherein one of the pair of bit lines associated with each read/write memory cell in the row corresponding to the decoded row address is discharged responsive to the turning on of the pass transistors in that read/write memory cell.

16. The method of claim 12 , further comprising:

writing, into a first location of a configuration register, a digital value indicating a first number of read-tracking memory cells to be coupled to the reference word line.

17. The method of claim 16 , further comprising:

writing, into a second location of the configuration register, a digital value indicating a second number of read-tracking memory cells coupled to the reference word line;

in a normal operating mode, coupling the number of read-tracking cells indicated by the first location of the configuration register to the reference word line; and

in a test mode, coupling the number of read-tracking cells indicated by the second location of the configuration register to the reference word line.