Multi-dimentional data randomization
The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.
1. A method comprising:
randomizing data addressed to a first row of a data array using at least a first scrambling sequence; and
randomizing data addressed to a second adjacent row of the data array using at least a second scrambling sequence that is a circular shift of the first scrambling sequence, wherein at least one of the first and second scrambling sequences include at least a portion of a maximum-length sequence (m-sequence) generated based on a seed of a length (N), wherein N is an integer greater than or equal to 1, the m-sequence having a length 2 N-1 .
2. The method of claim 1 , further comprising randomizing the data addressed to the first row of the data array using a first plurality of scrambling sequences, and randomizing the data addressed to the second adjacent row of the data array using a second plurality of scrambling sequences, wherein each of the second plurality of scrambling sequences is a circular shift of the one of the first plurality of scrambling sequences.
3. The method of claim 1 , further comprising randomizing a first column of the data array using a portion of the first scrambling sequence and randomizing a second column of the data array using first portion of the second scrambling sequence.
4. The method of claim 1 , wherein the circular shift is a single digit shift.
5. The method of claim 1 , wherein the circular shift is a shift of multiple digits.
6. The method of claim 1 , further comprising:
randomizing data of a third row of the data array using a third scrambling sequence that is a circular shift of the second scrambling sequence, the third row being adjacent to the second row.
7. The method of claim 1 , wherein the m-sequence includes every possible binary combination in 2 N states exactly once.
8. The method of claim 1 , wherein the scrambling sequence is stored in a hardware register of a memory controller that writes data to the data array.
9. The method of claim 1 , wherein a portion of the scrambling sequence for a first bitline is equal to a portion of the scrambling sequence of a first wordline.
10. The method of claim 1 , wherein the memory array is a 3D NAND array, and a same scrambling sequence is used to scramble each of a first bitline, a first wordline, and a first channel select line.
11. The method of claim 1 , wherein randomizing the data of the first row further comprises calculating a bit-wise Exclusive OR (XOR) between the data addressed to the first row and the first scrambling sequence.
12. A processor-implemented method comprising:
randomizing data addressed to a first row of a memory array using a number (M) of initial scrambling sequences, each of the initial scrambling sequences including at least a portion of a maximum-length sequence (m-sequence) generated based on a seed of a length (N), the m-sequence having a length 2 N-1 , wherein M and N are both integers greater than or equal to 1;
circularly shifting each of the M number of initial scrambling sequences; and
randomizing data addressed to a second adjacent row of the memory array using the circularly shifted scrambling sequences.
13. The processor-implemented method of claim 12 , wherein the memory array is a triple-level cell array and the M number of initial scrambling sequences consists of three scrambling sequences.
14. The processor-implemented method of claim 12 , the memory array is a multi-level cell array and the M number of initial scrambling sequences consists of two scrambling sequences.
15. The processor-implemented method of claim 12 , wherein the M number of scrambling sequences are stored in a hardware register of a memory controller that writes data to the memory array.
16. The processor-implemented method of claim 12 , wherein at least one of the M number of scrambling sequences is a maximum-length sequence dynamically generated by a shift register.
17. Apparatus comprising:
a memory controller configured to randomize data addressed to a first row of a data array using a first scrambling sequence and randomize data addressed to a second adjacent row of the data array using a second scrambling sequence, the second scrambling sequence being a circular shift of the first scrambling sequence, wherein at least one of the first and second scrambling sequences include at least a portion of a maximum-length sequence (m-sequence) generated based on a seed of a length (N), the m-sequence having a length 2 N-1 , wherein N is an integer greater than or equal to 1.
18. The apparatus of claim 17 , wherein the first column of the data array is randomized using a first portion of the first scrambling sequence and the second column of the data array is randomized using a first portion of the second scrambling sequence.
19. The apparatus of claim 17 , wherein the circular shift is a single digit shift.
20. The apparatus of claim 17 , wherein the first scrambling sequence is used to randomize three dimensions of data in the data array.