Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices

1. A system, comprising:

a silicon carbide (SiC) semiconductor device, the SiC semiconductor device having a source electrode disposed on top of a top surface of an interlayer dielectric and no intervening layer disposed between the interlayer dielectric and the source electrode; and

a hermetically sealed packaging enclosing the SiC semiconductor device, wherein the hermetically sealed packaging is configured to maintain an atmosphere around the SiC semiconductor device, wherein the atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation, wherein the threshold voltage is a voltage difference between a gate and source at a given source to drain current.

2. The system of claim 1 , wherein the atmosphere comprises a vacuum.

3. The system of claim 2 , wherein the vacuum comprises a pressure less than approximately 1 torr.

4. The system of claim 2 , wherein the vacuum comprises a pressure of approximately 0.1 torr.

5. The system of claim 1 , wherein the atmosphere comprises argon, helium, nitrogen, krypton, xenon, or a combination thereof.

6. The system of claim 1 , wherein the SiC semiconductor device comprises a metal-oxide field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a MOS controlled thyristor, or a gate controlled thyristor.

7. The system of claim 1 , wherein the packaging comprises an enclosure disposed about the SiC semiconductor device, wherein the enclosure is configured to surround the SiC semiconductor device in a reduced pressure environment relative to an environment outside of the enclosure, and wherein the reduced pressure environment reduces a threshold voltage shift of the SiC semiconductor device during operation.

8. The system of claim 7 , wherein the reduced pressure environment comprises a reduced pressure of an inert gas, wherein the inert gas comprises helium, argon, or nitrogen.

9. The system of claim 1 , wherein the packaging is formed of metal, polymer, or composite material.

10. The system of claim 9 , wherein the packaging is rigid.

11. The system of claim 9 , wherein the packaging is formed of a plurality of pieces and edges between the pieces are hermetically sealed.

12. The system of claim 11 , wherein the edges are sealed by welds.

13. The system of claim 11 , wherein the edges are sealed by solder.

14. The system of claim 11 , wherein the edges are sealed by glue, resin or epoxy.

15. The system of claim 11 , wherein the edges are sealed by melted portions of the pieces that have cooled.

16. The system of claim 9 , wherein the packaging comprises a unity polymer layer.

17. A completed silicon carbide (SiC) semiconductor device, comprising:

a source electrode disposed directly on top of a top surface of an interlayer dielectric and no intervening layer disposed between the interlayer dielectric and the source electrode; and

an atmosphere surrounding the SiC semiconductor device, wherein the atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation, wherein the threshold voltage is a voltage difference between a gate and source at a given source to drain current.

18. The SiC semiconductor device of claim 17 , wherein the SiC semiconductor device comprises a metal-oxide field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a MOS controlled thyristor, or a gate controlled thyristor.

19. The SiC semiconductor device of claim 17 , wherein the atmosphere comprises a vacuum.

20. The SiC semiconductor device of claim 19 , wherein the vacuum comprises a pressure less than approximately 1 torr.

21. The SiC semiconductor device of claim 19 , wherein the vacuum comprises a pressure of approximately 0.1 torr.

22. The SiC semiconductor device of claim 17 , wherein the atmosphere comprises argon, helium, nitrogen, krypton, xenon, or a combination thereof.