IP Library › Granted Patent US 9,576,965
Granted Patent B2
US 9,576,965 · App. 14/754,589 · Granted Feb 21, 2017

Semiconductor device and method for fabricating the same

Inventors: Jae Man Yoon (Seoul, KR); Young Bog Kim (Yongin, KR); Yun Seok Chun (Seongnam, KR); Woong Choi (Seoul, KR); Woo Jun Lee (Icheon, KR)
Assignee: SK HYNIX INC.
H01L27/10885H01L21/02282H01L21/28525H01L21/31144H01L21/768H01L27/0207H01L27/1085H01L27/10814H01L27/10823H01L27/10855H01L27/10894
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Quick Facts
Patent No.
US 9,576,965
App. No.
14/754,589
Granted
Feb 21, 2017
Kind
B2
Abstract

A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line.

Claims (28)

1. A method for forming a semiconductor device, the method comprising:

forming first and second bit lines spaced apart from each other by a first distance over a semiconductor substrate;

forming first and second supporting films spaced apart from each other by a second distance in a direction perpendicular to the first and second bit lines;

forming a first storage node contact and a second storage node contact between the first supporting film and the second supporting film, after forming the first and second supporting films, so that the first and second storage node contacts are supported by the first and second supporting films; and

etching upper portions of the second storage node contact and the first and second supporting films in a diagonal direction across the first and second bit lines at the same time.

2. The method according to claim 1 , wherein forming the first and second supporting films includes:

forming an interlayer insulation film to fill a space between the first bit line and the second bit line;

forming a capping film over the first and second bit lines and the interlayer insulation film;

forming first and second holes spaced apart from each other by the second distance in a direction perpendicular to the first and second bit lines;

forming the first supporting film and the second supporting film by filling the first hole and the second hole with an insulation material; and

removing the interlayer insulation film and the capping film.

3. The method according to claim 2 , wherein, in the forming of the first and second supporting film, the first hole and the second hole are formed in a cell region using a cell-opening mask.

4. The method according to claim 1 , wherein forming the first and second storage node contacts includes:

forming the first storage node contact at a lower part of a region surrounded by the first and second supporting films and the first and second bit lines; and

forming the second storage node contact over the first storage node contact and the first and second bit lines.

5. The method according to claim 4 , wherein a top surface of the second storage node contact is located at substantially the same level as the top surfaces of the first and second supporting films or located below the top surfaces of the first and second supporting films.

6. The method according to claim 1 , wherein the first storage node contact is formed of a polysilicon material, and the second storage node contact is formed of a metal material.

7. The method according to claim 1 , wherein the patterning includes:

patterning the second storage node using a Spacer Patterning Technology (SPT) or a Double Patterning Technology (DPT).

8. The method according to claim 1 , wherein the patterning includes:

sequentially depositing a first interlayer insulation film, a first etch stop film, a second interlayer insulation film, and a second etch stop film over the second storage node contact and the first and second supporting films;

forming first patterns by etching the second etch stop film and the second interlayer insulation film;

depositing a spacer material along a step difference of the first patterns;

depositing a Spin On Carbon (SOC) material in a space disposed between the first patterns on which the spacer material is deposited;

forming second patterns by etching the spacer material and the first etch stop film;

forming third patterns by etching the first interlayer insulation film using the second patterns as a mask; and

patterning the upper portions of the second storage node contact and the first and second supporting films using the third patterns as a mask.

9. The method according to claim 8 , wherein a distance between the first patterns is at least two times greater than a distance between the second patterns.

Priority Claims (1)
KR 10-2013-0128665 · Oct 28, 2013 · national
Continuity (2)
Continuation 14229612 · Mar 28, 2014
Related Publication 20150380415A1 · Dec 31, 2015