Non-volatile memory device and method of fabricating the same

1. A non-volatile memory device comprising:

an isolation layer formed in a substrate to define an active region;

a control plug formed over the isolation layer;

a floating gate formed over the isolation layer and being separated from the control plug by a first gap, and the floating gate extending over the active region;

a junction region formed in the active region and on both sides of the floating gate; and

contact plugs formed over the junction regions, where each of the contact plugs is separated from the floating gate by a second gap and a width of the first gap is smaller than a width of the second gap,

wherein the control plug only overlaps with the isolation layer and the floating gate overlaps with both the isolation layer and the active region, and

the floating gate is bent to have a first portion which extends in a first direction and a second portion which is in contact with the first portion and extends in a second direction crossing the first direction, where the first portion and the second portion of the floating gate face different sidewalls of the control plug, respectively.

2. The non-volatile memory device of claim 1 , further comprising:

a first charge blocking layer formed over sidewalls of the flowing gate; and

a second charge blocking layer formed over sidewalls of the control plug and the contact plugs.

3. The non-volatile memory device of claim 2 , wherein the first charge blocking layer and the second charge blocking layer are spacers.

4. The non-volatile memory device of claim 1 , wherein areas of facing sidewalls of the floating gate and the control plug are greater than areas of facing sidewalls of the floating gate and the contact plug.

5. The non-volatile memory device of claim 1 , wherein the control plug includes at least two plugs having sidewalls facing the sidewalls of the floating gate.

6. The non-volatile memory device of claim 1 , wherein the floating gate is controlled in response to a bias applied to the control plug.

7. The non-volatile memory device of claim 1 , wherein the first gap is filled with a double-layered insulating structure and the second gap is filled with a triple-layered insulating structure.

8. The non-volatile memory device of claim 2 , wherein the first charge blocking layer and the second charge blocking layer fills the first gap while not filling the second gap.

9. The non-volatile memory device of claim 8 , further comprising:

an insulating layer interposed between the first charge blocking layer and the second charge blocking layer to fill a remaining space of the second gap.

10. A non-volatile memory device comprising:

an isolation layer formed in a substrate to define a plurality of active regions;

a plurality of control plugs symmetrically arranged, over the isolation layer, with respect to the plurality of active regions;

a plurality of floating gates asymmetrically arranged with respect to the plurality of active regions, each floating gate, of the plurality of floating gates, and being separated from a corresponding control plug by a first gap, and each floating gate, of the plurality of floating gates, extending over a corresponding active region;

a plurality of junction regions formed in each active region, of the plurality of active regions, between the plurality of floating gates; and

a contact plug formed over each junction region, of the plurality of junction regions where the contact plug is separated from each floating gate by a second gap and a width of the first gap is smaller than a width of the second gap,

wherein the plurality of control plugs only overlap with the isolation layer, and each floating gate, of the plurality of floating gates, overlaps with both the isolation layer and the corresponding active region, and

each floating gate is bent to have a first portion which extends in a first direction and a second portion which is in contact with the first portion and extends in a second direction crossing the first direction, where the first portion and the second portion of each floating gate face different sidewalls of the corresponding control plug, respectively.

11. The non-volatile memory device of claim 10 , further comprising:

a first charge blocking layer formed over sidewalls of each floating gate; and

a second charge blocking layer formed on the sidewalls of each control plug.

12. The non-volatile memory device of claim 10 , wherein areas of facing sidewalls of each floating gate, of the plurality of floating gates, and each control plug, of the plurality of control plugs, are greater than areas of facing sidewalls of each floating gate, of the plurality of floating gates, and each contact plug.

13. The non-volatile memory device of claim 10 , wherein each floating gate, of the plurality of floating gates, has sidewalls facing a portion of or entire sidewalls of each control plug.

14. The non-volatile memory device of claim 10 , wherein each control plug includes at least two plugs having sidewalls facing the sidewalls of each floating gate, of the plurality of floating gates.

15. The non-volatile memory device of claim 10 , wherein the plurality of floating gates are controlled in response to a bias applied to the plurality of control plugs.

16. The non-volatile memory device of claim 11 , wherein the first charge blocking layer and the second charge blocking layer fills the first gap while not filling the second gap.

17. The non-volatile memory device of claim 16 , further comprising:

an insulating layer interposed between the first charge blocking layer and the second charge blocking layer to fill a remaining space of the second gap.

18. The non-volatile memory device of claim 10 , wherein the first gap is filled with a double-layered insulating structure and the second gap is filled with a triple-layered insulating structure.