Source/drain regions for fin field effect transistors and methods of forming same

1. A method for forming a semiconductor device, the method comprising:

forming a fin extending upwards from a semiconductor substrate;

forming a sacrificial layer on sidewalls of a portion of the fin;

forming a spacer layer over the sacrificial layer;

recessing the portion of the fin past a bottom surface of the sacrificial layer, wherein the recessing forms a trench disposed between sidewall portions of the spacer layer;

removing at least a portion of the sacrificial layer under the spacer layer; and

forming a source/drain region in the trench.

2. The method of claim 1 , wherein forming the source/drain region in the trench comprises an epitaxially growing the source/drain region.

3. The method of claim 2 , wherein removing at least the portion of the sacrificial layer defines openings under the spacer layer, and wherein epitaxially growing the source/drain region comprises flowing a precursor through the openings into the trench.

4. The method of claim 3 , wherein the fin is disposed adjacent a shallow trench isolation (STI) region, wherein removing at least the portion of the sacrificial layer forms the openings between a bottom surface of the spacer layer and the STI region.

5. The method of claim 1 further comprising forming a gate stack over sidewalls and a top surface of a channel region of the fin, wherein forming the sacrificial layer and the spacer layer comprises forming the sacrificial layer and the spacer layer on sidewalls of the gate stack.

6. The method of claim 1 wherein forming the sacrificial layer comprises depositing the sacrificial layer on a top surface and sidewalls of the portion of the fin, wherein forming the spacer layer comprises depositing the spacer layer on a top surface and sidewalls of the sacrificial layer, and wherein recessing the portion of the fin comprises exposing the portion of the fin by removing top portions of the sacrificial layer and the spacer layer.

7. A method for forming a semiconductor device, the method comprising:

forming a first semiconductor fin;

forming a plurality of sidewall spacers, wherein the first semiconductor fin is disposed between first adjacent ones of the plurality of sidewall spacers;

forming openings under a bottom surface of the plurality of sidewall spacers;

forming a first trench between the first adjacent ones of the plurality of sidewall spacers; and

epitaxially growing a first source/drain region in the first trench over the first semiconductor fin, wherein epitaxially growing the first source/drain region comprises flowing a precursor into the first trench through the openings.

8. The method of claim 7 , wherein forming openings under a bottom surface of the plurality of sidewall spacers comprises:

forming a sacrificial layer between the plurality of sidewall spacers and the first semiconductor fin, wherein the sacrificial layer extends under the bottom surface of the plurality of sidewall spacers; and

removing at least a portion of the sacrificial layer.

9. The method of claim 7 , wherein epitaxially growing the first source/drain regions further comprises flowing the precursor into the first trench between the first adjacent ones of the plurality of sidewall spacers.

10. The method of claim 7 further comprising:

forming a second semiconductor fin, wherein the second semiconductor fin is disposed between second adjacent ones of the plurality of sidewall spacers;

defining a second trench the second adjacent ones of the plurality of sidewall spacers;

epitaxially growing a second source/drain region in the second trench over the second semiconductor fin, wherein epitaxially growing the second source/drain region comprises:

flowing a precursor into the second trench through the openings; and

forming an epitaxy region connecting the first and the second source/drain regions.

11. The method of claim 10 , wherein the epitaxy region extends upwards along sidewalls of the plurality of sidewall spacers.

12. The method of claim 7 , wherein forming the first trench comprises recessing the first semiconductor fin past a top surface of a shallow trench isolation (STI) region.

13. The method of claim 7 , further comprising:

forming a gate stack on a top surface and a sidewalls of a portion of the first semiconductor fin; and

forming gate spacers on sidewalls of the gate stack, wherein the plurality of sidewall spacers are connected to and structurally supported by the gate spacers while forming openings under the bottom surface of the plurality of sidewall spacers.

14. A method comprising:

forming a fin extending upwards from a semiconductor substrate, wherein the fin is disposed adjacent to and extends above a shallow trench isolation (STI) region;

depositing a sacrificial layer over a top surface and along sidewalls of a first portion of the fin, wherein the sacrificial layer is further deposited over a top surface of the STI region;

depositing a spacer layer over the sacrificial layer, over the top surface of the first portion of the fin, over the top surface of the STI region, and along the sidewalls of the first portion of the fin;

removing lateral portions of the sacrificial layer and the spacer layer to expose the first portion of the fin and the top surface of the STI region, wherein removing lateral portions of the spacer layer defines sidewall spacers along opposing sides of the first portion of the fin;

removing the first portion of the fin to define a trench between the sidewall spacers;

removing remaining portions of the sacrificial layer to define an opening between a first one of the sidewall spacers and the STI region; and

epitaxially growing semiconductor material in the trench.

15. The method of claim 14 , wherein epitaxially growing the semiconductor material comprises flowing a precursor chemical into the trench through the opening.

16. The method of claim 14 further comprising:

forming a gate stack on a top surface and a sidewalls of a second portion of the fin; and

forming gate spacers on sidewalls of the gate stack, wherein the sidewall spacers are connected to and structurally supported by the gate spacers while removing the remaining portions of the sacrificial layer.

17. The method of claim 16 , wherein the gate stack masks the second portion of the fine while removing the first portion of the fin.

18. The method of claim 14 , wherein epitaxially growing the semiconductor material comprises epitaxially growing the semiconductor material between the sidewall spacer and the STI region.

19. The method of claim 14 , wherein epitaxially growing the semiconductor material comprises epitaxially growing the semiconductor material along opposing sidewalls of the first one of the sidewall spacers.

20. The method of claim 14 , wherein epitaxially growing the semiconductor material comprises epitaxially growing the semiconductor material to cover an entire top surface of the STI region.