IP Library › Granted Patent US 9,577,635

Granted Patent B2

US 9,577,635 · App. 14/598,182 · Granted Feb 21, 2017

Clock-gating cell with low area, low power, and low setup time

Inventors: Seid Hadi Rasouli (San Diego, CA); Steven James Dillen (San Diego, CA); Animesh Datta (San Diego, CA)

Assignee: QUALCOMM INCORPORATED

H03K19/0016 H03K17/6872

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Quick Facts

Patent No.: US 9,577,635
App. No.: 14/598,182
Granted: Feb 21, 2017
Kind: B2

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Abstract

A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Claims (80)

1. A clock-gating cell, comprising:

an enable module comprising a NOR gate that receives an enable module input and has an enable module output; and

a latch module having latch module inputs and a latch module output, the latch module inputs including a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output, the latch module enable input being coupled to the enable module output, the latch module being configured to enable and to disable the clock via the latch module output based on the enable module input,

wherein the latch module comprises:

a first p-type metal oxide semiconductor (pMOS) transistor having a first pMOS transistor source, a first pMOS transistor drain, and a first pMOS transistor gate, the first pMOS transistor source being coupled to a first voltage source, the first pMOS transistor drain being coupled to a first node; and

a second pMOS transistor having a second pMOS transistor source, a second pMOS transistor drain, and a second pMOS transistor gate, the second pMOS transistor source being coupled to the first node, the second pMOS transistor drain being coupled to an internal enable node, the internal enable node being the latch module output, the second pMOS transistor gate being coupled to the enable module output, wherein the first pMOS transistor gate is configured to receive functionally ĒC, where E is the internal enable node and C is the clock.

2. The clock-gating cell of claim 1 , wherein the enable module input comprises at least two inputs including a clock enable input and a test enable input.

3. The clock-gating cell of claim 1 , wherein the latch module further comprises a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor drain, and a first nMOS transistor gate, the first nMOS transistor source being coupled to a second voltage source, the first nMOS transistor drain being coupled to a second node, and the first nMOS transistor gate being coupled to the enable module output.

4. The clock-gating cell of claim 3 , wherein the clock-gating cell further comprises a NAND gate having NAND gate inputs coupled to the clock and the internal enable node, and a NAND gate output coupled to a third node.

5. A clock-gating cell, comprising:

an enable module comprising a NOR gate that receives an enable module input and has an enable module output; and

wherein the latch module comprises:

a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor drain, and a first nMOS transistor gate, the first nMOS transistor source being coupled to a second voltage source, the first nMOS transistor drain being coupled to a second node, and the first nMOS transistor gate being coupled to the enable module output;

a third pMOS transistor having a third pMOS transistor source coupled to the first voltage source, a third pMOS transistor drain coupled to the internal enable node, and a third pMOS transistor gate coupled to a third node; and

a second nMOS transistor having a second nMOS transistor source coupled to the second node, a second nMOS transistor drain coupled to the internal enable node, and a second nMOS transistor gate coupled to the third node.

6. The clock-gating cell of claim 5 , wherein the clock-gating cell further comprises an inverter coupled between the third node and an output of the clock-gating cell.

7. The clock-gating cell of claim 5 , wherein the first pMOS transistor gate is coupled to the clock.

8. The clock-gating cell of claim 7 , wherein the latch module further comprises:

a third nMOS transistor having a third nMOS transistor source coupled to a fourth node, a third nMOS transistor drain coupled to the second node, and a third nMOS transistor gate coupled to a fifth node;

a fourth nMOS transistor having a fourth nMOS transistor source coupled to the second voltage source, a fourth nMOS transistor drain coupled to the fourth node, and a fourth nMOS transistor gate coupled to the clock; and

an inverter coupled between the internal enable node and the fifth node.

9. A clock-gating cell, comprising:

an enable module having an enable module input and an enable module output; and

wherein the latch module includes an internal enable node that is the latch module output, and the latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and a node of a function Ē AND C, where E is the internal enable node and C is the clock; and

a gate to enable and disable the clock by a function of EC.

10. A clock-gating cell, comprising:

an enable module having an enable module input and an enable module output; and

wherein the latch module further comprises:

wherein the first pMOS transistor gate is configured to receive functionally Ē AND C, where E is the internal enable node and C is the clock.

11. The clock-gating cell of claim 10 , wherein the enable module comprises a NOR gate, the NOR gate receiving the enable module input, the enable module input comprising at least two inputs including a clock enable input and a test enable input.

12. The clock-gating cell of claim 10 , wherein the latch module further comprises a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor drain, and a first nMOS transistor gate, the first nMOS transistor source being coupled to a second voltage source, the first nMOS transistor drain being coupled to a second node, and the first nMOS transistor gate being coupled to the enable module output.

13. The clock-gating cell of claim 12 , wherein the clock-gating cell further comprises a NAND gate having NAND gate inputs coupled to the clock and the internal enable node, and a NAND gate output coupled to a third node.

14. The clock-gating cell of claim 12 , wherein the latch module further comprises:

15. The clock-gating cell of claim 14 , wherein the clock-gating cell further comprises an inverter coupled between the third node and an output of the clock-gating cell.

16. The clock-gating cell of claim 14 , wherein the latch module further comprises a third nMOS transistor having a third nMOS transistor source coupled to the second voltage source, a third nMOS transistor drain coupled to the second node, and a third nMOS transistor gate coupled to a fourth node.

17. The clock-gating cell of claim 16 , wherein the first pMOS transistor gate is coupled to the fourth node.

18. The clock-gating cell of claim 16 , wherein the latch module further comprises:

an inverter coupled between the clock and a fifth node; and

a NOR gate having NOR gate inputs and a NOR gate output, the NOR gate inputs being coupled to the internal enable node and the fifth node, the NOR gate output being coupled to the fourth node.

19. A method of operation of a clock-gating cell, comprising:

enabling, at an enable module, a latch module at an enable module output based on an enable module input;

latching, at the latch module, a state at an internal enable node within the latch module based on the enable module input in order to enable and to disable a clock, wherein the internal enable node transitions from low to high as a function of the enable module output and a node of a function Ē AND C, where E is the internal enable node and C is the clock, and

wherein the clock is enabled or disabled via a gate of a function of EC.

20. A method of operation of a clock-gating cell, comprising:

enabling, at an enable module, a latch module at an enable module output based on an enable module input; and

wherein the first pMOS transistor gate is configured to receive functionally Ē AND C.

21. The method of claim 20 , wherein the enable module comprises a NOR gate, the NOR gate receiving the enable module input, the enable module input comprising at least two inputs including a clock enable input and a test enable input.

22. The method of claim 20 , wherein the latch module further comprises a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor drain, and a first nMOS transistor gate, the first nMOS transistor source being coupled to a second voltage source, the first nMOS transistor drain being coupled to a second node, and the first nMOS transistor gate being coupled to the enable module output.

23. The method of claim 22 , wherein the clock-gating cell further comprises a NAND gate having NAND gate inputs coupled to the clock and the internal enable node, and a NAND gate output coupled to a third node.

24. The method of claim 22 , wherein the latch module further comprises:

25. A clock-gating cell, comprising:

means for enabling a means for latching at an enable module output based on an enable module input;

means for latching a state at an internal enable node within the means for latching based on the enable module input in order to enable and to disable a clock, wherein the internal enable node transitions from low to high as a function of the enable module output and a node of a function Ē AND C, where E is the internal enable node and C is the clock; and

a gate to enable and disable the clock by a function of EC.

26. A clock-gating cell, comprising:

means for enabling a means for latching at an enable module output based on an enable module input; and

wherein the first pMOS transistor gate is configured to receive functionally Ē AND C.

27. The clock-gating cell of claim 26 , wherein the means for enabling comprises a NOR gate, the NOR gate receiving the enable module input, the enable module input comprising at least two inputs including a clock enable input and a test enable input.

28. The clock-gating cell of claim 26 , wherein the means for latching further comprises a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor source, a first nMOS transistor drain, and a first nMOS transistor gate, the first nMOS transistor source being coupled to a second voltage source, the first nMOS transistor drain being coupled to a second node, and the first nMOS transistor gate being coupled to the enable module output.

29. The clock-gating cell of claim 28 , wherein the means for latching further comprises:

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015

From: RASOULI, SEID HADI; DILLEN, STEVEN JAMES; DATTA, ANIMESH

To: QUALCOMM INCORPORATED

Reel/Frame 035021/0434 →

Continuity (1)

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