Metal gate structure and manufacturing method thereof
The present disclosure provides a semiconductor structure includes a semiconductor layer having a first surface, and an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a barrier layer, and a work function metal layer. A thickness of a first portion of the barrier layer at the sidewall of the metal gate is substantially thinner than a thickness of the barrier layer at the bottom of the metal gate. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate trench in an ILD, forming a barrier layer in a bottom and a sidewall of the metal gate trench, removing a first portion of the barrier layer at the sidewall of the metal gate trench, and forming a work function metal layer conforming to the barrier layer.
1. A semiconductor structure, comprising:
a semiconductor layer having a first surface; and
an interlayer dielectric (ILD) defining a metal gate over the first surface of the semiconductor layer, wherein the metal gate comprises:
a high-k dielectric layer conforming to a bottom and a sidewall of the metal gate;
a barrier layer without aluminum conforming to the high-k dielectric layer, a portion of the high-k dielectric layer at the bottom of the metal gate not being covered by the barrier layer;
a work function metal layer containing aluminum conforming to the barrier layer and the high-k dielectric layer; and
a gate fill metal surrounded by the work function metal layer, and wherein the work function metal layer is located between the gate fill metal and the high-k dielectric layer.
2. The semiconductor structure in claim 1 , no barrier layer is at the sidewall of the metal gate.
3. The semiconductor structure in claim 1 , wherein the barrier layer comprises a bilayer.
4. The semiconductor structure in claim 1 , wherein a thickness of the barrier layer is in a range of from about 2 {acute over (Å)} to about 40 {acute over (Å)}.
5. The semiconductor structure in claim 1 , wherein a tail of the work function metal layer, which is the most proximal portion of the work function metal layer with respect to the bottom corner of the metal gate, has a bottom surface in direct contact with the high-k dielectric layer at the bottom of the metal gate.
6. A semiconductor structure, comprising:
a high-k dielectric layer conforming to a bottom and a sidewall of a metal gate;
a barrier layer without aluminum conforming to a bottom of the high-k dielectric layer, a portion of the bottom of the high-k dielectric layer not being covered by the barrier layer;
a work function metal layer containing aluminum conforming to the barrier layer and the high-k dielectric layer, wherein a tail of the work function metal layer, which is the most proximal portion of the work function metal layer with respect to the bottom corner of the metal gate, has a bottom surface in direct contact with the bottom of high-k dielectric layer; and
a gate fill metal surrounded by the work function metal layer.
7. The semiconductor structure in claim 6 , wherein the barrier layer is a bilayer between the work function metal layer and the high-k dielectric layer.
8. The semiconductor structure in claim 6 , wherein a thickness of the barrier layer is of from about 2 {acute over (Å)} to about 40 {acute over (Å)}.
9. The semiconductor structure in claim 6 , wherein the semiconductor structure is an N-MOSFET or an N-FinFET.
10. A method for manufacturing a semiconductor structure, comprising;
forming a metal gate trench in an interlayer dielectric (ILD);
forming a barrier layer without aluminum in a bottom and a sidewall of the metal gate trench;
removing a sidewall portion of the barrier layer;
forming a work function metal layer containing aluminum, conforming to the barrier layer; and
overfilling a gate fill metal to level the gate trench.
11. The method for manufacturing a semiconductor structure in claim 10 , wherein the removing the sidewall portion comprises:
filling an etchable material in the metal gate trench;
etching back the etchable material to at least partially expose the sidewall portion of the barrier layer;
removing the sidewall portion of the barrier layer; and
removing the remaining etchable material.
12. The method for manufacturing a semiconductor structure in claim 10 , further comprising removing the overfilled gate fill metal and the work function metal layer from a top surface of the ILD.
13. The method for manufacturing a semiconductor structure in claim 10 , further comprising an ion implantation operation after the formation of the work function metal layer.
14. The method for manufacturing a semiconductor structure in claim 13 , wherein the ion implantation operation comprises implanting aluminum into the work function metal layer.
15. The method for manufacturing a semiconductor structure in claim 11 , wherein the etchable material is selected from at least one in the group consisting of spin-on glass (SOG), photoresist, oxide, and boro-phospho-silicate-glass (BPSG).
16. The method for manufacturing a semiconductor structure in claim 11 , wherein the removing the sidewall portion of the barrier layer comprises performing a wet etch operation or a dry etch operation selective between a nitride and an oxide.
17. The method for manufacturing a semiconductor structure in claim 11 , wherein the removing a sidewall portion of the barrier layer comprises an over-etch operation.
18. The method for manufacturing a semiconductor structure in claim 17 , wherein the over-etch operation removes the sidewall portion of the barrier layer until a sidewall of the etchable material is exposed.
19. The method for manufacturing a semiconductor structure in claim 17 , wherein the over-etch operation removes the sidewall portion of the barrier layer until a portion of the bottom of the metal gate trench is exposed.