Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow
An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
1. A method of forming an integrated circuit, comprising the steps:
extending NMOS gate overhang of active on NMOS transistors in the integrated circuit beyond a minimum NMOS gate overhang of active design rule;
reducing the PMOS gate overhang of active on PMOS transistors to a minimum PMOS gate overhang of active design rule; and
forming dual stress liners on the integrated circuit where a dual stress liner (DSL) boundary lies between the NMOS transistors and the PMOS transistors, wherein the step of extending the NMOS gate overhang of active causes the NMOS gate overhang of active to cross the DSL boundary.
2. The method of claim 1 , wherein the NMOS transistor is an NMOS transistor with a width that is smaller than an adjacent NMOS transistor and where the step of extending involves removing a gap between a gate of the NMOS transistor and an OPC dummy gate extension.
3. The method of claim 1 , wherein the PMOS transistor is a PMOS transistor with a width that is smaller than an adjacent PMOS transistor and where the step of minimizing involves forming a gap between a gate of the PMOS transistor and an OPC dummy gate extension and wherein the PMOS transistor gate next to the gap overhangs the active by the minimum PMOS gate overhang of active design rule.
4. The method of claim 1 , wherein the gate overhang of active for the NMOS transistor is extended to a length in the range of 50 nm to 200 nm.
5. A method of forming an integrated circuit, comprising the steps:
forming an NMOS gate of an NMOS transistor over a first active region;
forming a PMOS gate of a PMOS transistor over a second active region;
and forming dual stress liners on the integrated circuit where a first dual stress liner (DSL) boundary lies between the NMOS transistor and the PMOS transistor, wherein:
the NMOS gate includes an NMOS gate extension that extends past an edge of the first active region nearest the DSL boundary a first distance;
the PMOS gate includes a PMOS gate extension that extends past an edge of the second active region nearest the DSL boundary a second distance; and
the first distance is greater than the second distance.
6. The method of claim 5 , wherein forming the dual stress liners forms a second DSL boundary adjacent the NMOS transistor opposite the first DSL boundary and the NMOS gate extension extends past the second DSL boundary.
7. The method of claim 5 , wherein forming the dual stress liners forms a second DSL boundary adjacent the NMOS transistor opposite the first DSL boundary and the NMOS gate extension extends past an edge of the first active region nearest the second DSL boundary a third distance greater than the first distance.
8. The method of claim 7 , wherein forming the dual stress liners forms a third DSL boundary adjacent the PMOS transistor opposite the first DSL boundary and the PMOS gate extension extends past an edge of the second active region nearest the third DSL boundary by a fourth distance equal to the second distance.