Semiconductor device
An improvement is achieved in the reliability of a semiconductor device having an IGBT. In an active cell region, in a portion of a semiconductor substrate which is interposed between first and second trenches in which first and second trench gate electrodes are embedded, an n + -type emitter region, a p-type body region located thereunder, and a first n-type hole barrier region located thereunder are formed. In a hole collector cell region, in a portion of the semiconductor substrate which is interposed between third and fourth trenches in which third and fourth trench gate electrodes are embedded, the p-type body region and a second n-type hole barrier region located thereunder are formed, but an n-type semiconductor region equivalent to the n + -type emitter region is not formed. Under the first and second n-type hole barrier regions, an n − -type drift region having an impurity concentration lower than those thereof is present. The impurity concentration of the second n-type hole barrier region is higher than the impurity concentration of the first n-type hole barrier region.
1. A semiconductor device having an IGBT, comprising:
a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first semiconductor region having a first conductivity type and formed in the semiconductor substrate to be closer to the second main surface;
a collector electrode formed over the second main surface of the semiconductor substrate to be electrically coupled to the first semiconductor region;
a second semiconductor region having a second conductivity type opposite to the first conductivity type and formed in the semiconductor substrate to be located over the first semiconductor region;
first and second trenches formed in the first main surface of the semiconductor substrate to face each other;
third and fourth trenches formed in the first main surface of the semiconductor substrate to face each other;
a first trench gate electrode formed in the first trench via a first gate insulating film;
a second trench gate electrode formed in the second trench via a second gate insulating film;
a first trench electrode formed in the third trench via a first insulating film;
a second trench electrode formed in the fourth trench via a second insulating film;
a third semiconductor region having the first conductivity type and formed in a portion of the semiconductor substrate which is interposed between the first and second trenches to be closer to the first main surface;
a fourth semiconductor region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the first and second trenches to be located in an upper portion of the third semiconductor region;
a fifth semiconductor region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the first and second trenches to be located under the third semiconductor region;
a sixth semiconductor region having the first conductivity type and formed in a portion of the semiconductor substrate which is interposed between the third and fourth trenches to be closer to the first main surface;
a seventh semiconductor region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the third and fourth trenches to be located under the sixth semiconductor region; and
an emitter electrode formed over the first main surface of the semiconductor substrate to be electrically coupled to the third, fourth, and sixth semiconductor regions;
wherein, in the portion of the semiconductor substrate which is interposed between the third and fourth trenches, a semiconductor region having the second conductivity type and electrically coupled to the emitter electrode is not formed over the sixth semiconductor region,
wherein the first and second trench electrodes are electrically coupled to the emitter electrode,
wherein the second semiconductor region is present under each of the fifth and seventh semiconductor regions,
wherein an impurity concentration of the fifth semiconductor region is higher than an impurity concentration of the second semiconductor region, and
wherein an impurity concentration of the seventh semiconductor region is higher than an impurity concentration of each of the second and fifth semiconductor regions.
2. The semiconductor device according to claim 1 ,
wherein the impurity concentration of the seventh semiconductor region is not less than double the impurity concentration of the fifth semiconductor region.
3. The semiconductor device according to claim 2 ,
wherein the impurity concentration of the seventh semiconductor region is not more than twenty-five times the impurity concentration of the fifth semiconductor region.
4. The semiconductor device according to claim 1 , further comprising:
an eight semiconductor region having the second conductivity type and interposed between the first and second semiconductor regions in the semiconductor substrate,
wherein an impurity concentration of the eighth semiconductor region is higher than the impurity concentration of the second semiconductor region.
5. The semiconductor device according to claim 1 , further comprising:
an interlayer insulating film formed over the first main surface of the semiconductor substrate so as to cover the first and second trench gate electrodes and the first and second trench electrodes;
a first opening located between the first and second trenches in plan view to extend through the interlayer insulating film and be cut in a part of the semiconductor substrate;
a second opening located between the third and fourth trenches in plan view to extend through the interlayer insulating film and be cut in a part of the semiconductor substrate;
a first coupling electrode electrically coupled to the emitter electrode and embedded in the first opening; and
a second coupling electrode electrically coupled to the emitter electrode and embedded in the second opening,
wherein the first coupling electrode is electrically coupled to the third and fourth semiconductor regions, and
wherein the second coupling electrode is electrically coupled to the sixth semiconductor region.
6. The semiconductor device according to claim 5 ,
wherein the first and second coupling electrodes are formed integrally with the emitter electrode.
7. The semiconductor device according to claim 5 , further comprising:
a ninth semiconductor region having the first conductivity type and formed in the third semiconductor region to be adjacent to a bottom surface of the first coupling electrode,
wherein an impurity concentration of the ninth semiconductor region is higher than an impurity concentration of the third semiconductor region, and
wherein the ninth semiconductor region is in contact with the fifth semiconductor region.
8. The semiconductor device according to claim 7 ,
wherein the ninth semiconductor region includes a tenth semiconductor region having the first conductivity type and adjacent to the bottom surface of the first coupling electrode and an eleventh semiconductor region having the first conductivity type and interposed between the tenth and fifth semiconductor regions, and
wherein an impurity concentration of the eleventh semiconductor region is higher than the impurity concentration of the third semiconductor region and lower than an impurity concentration of the tenth semiconductor region.
9. The semiconductor device according to claim 1 ,
wherein a bottom surface of the third semiconductor region is deeper than a bottom surface of the sixth semiconductor region.
10. The semiconductor device according to claim 1 ,
wherein each of the fifth and seventh semiconductor regions is a hole barrier semiconductor region.
11. The semiconductor device according to claim 1 ,
wherein the third, fourth, and fifth semiconductor regions are components of a unit IGBT.
12. The semiconductor device according to claim 1 ,
wherein the seventh and sixth semiconductor regions are components of a carrier discharge cell.
13. The semiconductor device according to claim 1 ,
wherein a depth of each of the third and fourth trenches is deeper than a depth of each of the first and second trenches.
14. The semiconductor device according to claim 1 ,
wherein a space between the third and fourth trenches is smaller than a space between the first and second trenches.
15. A semiconductor device having an IGBT, comprising:
a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a collector region having a first conductivity type and formed in the semiconductor substrate to be closer to the second main surface;
a collector electrode formed over the second main surface of the semiconductor substrate to be electrically coupled to the collector region;
a drift region having a second conductivity type opposite to the first conductivity type and formed in the semiconductor substrate to be located over the collector region;
first and second trenches formed in the first main surface of the semiconductor substrate to face each other;
third and fourth trenches formed in the first main surface of the semiconductor substrate to face each other;
a first trench gate electrode formed in the first trench via a first gate insulating film;
a second trench gate electrode formed in the second trench via a second gate insulating film;
a first trench electrode formed in the third trench via a first insulating film;
a second trench electrode formed in the fourth trench via a second insulating film;
a first body region having the first conductivity type and formed in a portion of the semiconductor substrate which is interposed between the first and second trenches to be closer to the first main surface;
a first emitter region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the first and second trenches to be located in an upper portion of the first body region;
a first hole barrier region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the first and second trenches to be located under the first body region;
a second body region having the first conductivity type and formed in a portion of the semiconductor substrate which is interposed between the third and fourth trenches to be closer to the first main surface;
a second hole barrier region having the second conductivity type and formed in the portion of the semiconductor substrate which is interposed between the third and fourth trenches to be located under the second body region; and
an emitter electrode formed over the first main surface of the semiconductor substrate to be electrically coupled to the first body region, the first emitter region, and the second body region;
wherein, in the portion of the semiconductor substrate which is interposed between the third and fourth trenches, an emitter region having the second conductivity type and electrically coupled to the emitter electrode is not formed over the second body region,
wherein the first and second trench electrodes are electrically coupled to the emitter electrode,
wherein the drift region is present under each of the first and second hole barrier regions,
wherein an impurity concentration of the first hole barrier region is higher than an impurity concentration of the drift region, and
wherein an impurity concentration of the second hole barrier region is higher than an impurity concentration of each of the drift region and the first hole barrier region.