Nonvolatile memory device including multi-plane
A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.
1. A nonvolatile memory device comprising:
a first plane disposed on a first semiconductor layer and including first cell strings and a first word line step region being adjacent to the first cell strings;
a second plane disposed on a second semiconductor layer and including second cell strings and a second word line step region being adjacent to the second cell strings;
a first address decoder configured to supply first operation voltages to the first plane;
a second address decoder configured to supply second operation voltages to the second plane;
a first peripheral circuit disposed between a substrate and the first semiconductor layer and configured to control the first address decoder; and
a second peripheral circuit disposed between the substrate and the second semiconductor layer and configured to control the second address decoder,
wherein the first peripheral circuit is disposed under the first word line step region, and the second peripheral circuit is disposed under the second word line step region.
2. The nonvolatile memory device of claim 1 , wherein the first cell strings are formed in a first direction orthogonal to the first semiconductor layer, and the second cell strings are formed in the first direction orthogonal to the second semiconductor layer.
3. The nonvolatile memory device of claim 2 , wherein the first word line step region includes first word lines which are stacked in the first direction as a step shape, and the second word line step region includes second word lines which are stacked in the first direction as a step shape.
4. The nonvolatile memory device of claim 1 , wherein the first address decoder is connected to the first cell strings via first word lines, and the second address decoder is connected the second cell strings via second word lines.
5. The nonvolatile memory device of claim 4 , wherein each of the first word lines is connected to a decoder conductive layer disposed on the first address decoder through a decoder via, and each of the second word lines is connected to a second decoder conductive layer disposed on the second address decoder through a decoder via.
6. The nonvolatile memory device of claim 1 , wherein the first peripheral circuit and second peripheral circuit are connected via a peripheral conductive layer disposed under the first word line step region and second word line step region.
7. The nonvolatile memory device of claim 6 , wherein an active region of at least one transistor included in the first peripheral circuit is connected to the peripheral conductive layer, and a gate region of at least one transistor included in the second peripheral circuit is connected to the peripheral conductive layer.
8. The nonvolatile memory device of claim 1 , further comprising:
a first page buffer circuit configured to program data to the first cell strings and read data from the first cell strings;
a second page buffer circuit configured to program data to the second cell strings and read data from the second cell strings,
wherein the first page buffer circuit is arranged adjacent to the first peripheral circuit on the substrate and the second page buffer circuit is arranged adjacent to the second peripheral circuit on the substrate.
9. The nonvolatile memory device of claim 8 , wherein the first page buffer circuit is connected to first bit lines connected to the first cell strings through a first page buffer via penetrating the first semiconductor layer, and
the second page buffer circuit is connected to second bit lines connected to the second cell strings through a second page buffer via penetrating the second semiconductor layer.
10. A nonvolatile memory device comprising:
a first plane including first cell strings disposed on a first semiconductor layer in a first direction orthogonal to the first semiconductor layer and including first and second substring groups dividing the first cell strings;
a second plane including second cell strings disposed on a second semiconductor layer in the first direction and including third and fourth substring groups dividing the second cell strings;
a first address decoder disposed between the first substring group and second substring group and configured to provide first operation voltages to the first plane;
a second address decoder disposed between the third substring group and forth substring group and configured to provide second operation voltages to the second plane;
a first peripheral circuit disposed between a substrate and the first plane and configured to control the first address decoder; and
a second peripheral circuit disposed between the substrate and the second plane and configured to control the second address decoder,
wherein the first plane includes a first word line step region being adjacent to the first cell strings and the second plane includes a second word line step region being adjacent to the second cell strings, and
the first peripheral circuit is disposed under the first word line step region and the second peripheral circuit is disposed under the second word line step region.
11. The nonvolatile memory device of claim 10 , wherein the first word line step region includes first word lines which are stacked in the first direction as a step shape, and the second word line step region includes second word lines which are stacked in the first direction as a step shape.
12. The nonvolatile memory device of claim 10 , wherein the first address decoder is connected to the first cell strings via first word lines, and the second address decoder is connected the second cell strings via second word lines.
13. The nonvolatile memory device of claim 12 , wherein each of the first word lines is connected to a decoder conductive layer disposed on the first address decoder through a decoder via, and each of the second word lines is connected to a second decoder conductive layer disposed on the second address decoder through a decoder via.
14. The nonvolatile memory device of claim 10 , wherein the first peripheral circuit and second peripheral circuit are connected via a peripheral conductive layer disposed under the first word line step region and second word line step region.
15. The nonvolatile memory device of claim 14 , wherein an active region of at least one transistor included in the first peripheral circuit is connected to the peripheral conductive layer, and a gate region of at least one transistor included in the second peripheral circuit is connected to the peripheral conductive layer.