Buffer stack for group IIIA-N devices
A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.
1. A power transistor device, comprising:
a substrate;
a multi-layer buffer stack comprising a plurality of buffer layers on said substrate including:
a first voided Group IIIA-N layer having a void density greater than 5 voids per square μm and an average void diameter between 0.05 to 0.2 μms on said substrate;
a first essentially void-free Group IIIA-N layer having a void density less than 5 voids per square μm and an average void diameter less than 0.05 μm on said first voided Group IIIA-N layer;
a first high roughness Group IIIA-N layer having a room mean squared (rms) roughness of at least 10 Å on said first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer having an rms roughness less than 10 Å on said first high roughness Group IIIA-N layer,
at least one Group IIIA-N surface layer on said first essentially smooth Group IIIA-N layer;
a source contact and a drain contact to said Group IIIA-N surface layer, and
a gate electrode on a gate dielectric on said Group IIIA-N surface layer.
2. The power transistor device of claim 1 , wherein said substrate comprises sapphire, silicon or silicon carbide (SiC).
3. The power transistor device of claim 1 , wherein said rms roughness of said first high roughness Group IIIA-N layer is from 15 Å to 50 Å and said rms roughness of said first essentially smooth Group IIIA-N layer is between 1 Å and 10 Å.
4. The power transistor device of claim 1 , wherein said multi-layer buffer stack further comprises:
a second voided Group IIIA-N layer having a void density greater than 5 voids per square μm and an average void diameter between 0.05 to 0.2 μms on said first essentially void-free Group IIIA-N layer;
a second essentially void-free Group IIIA-N layer having a void density less than 5 voids per square μm and an average void diameter less than 0.05 μm on said second voided Group IIIA-N layer;
a second high roughness Group IIIA-N layer having an rms roughness of at least 10 Å on said second essentially void-free Group IIIA-N layer, and
a second essentially smooth Group IIIA-N layer having an rms roughness less than 10 Å on said second high roughness Group IIIA-N layer,
wherein said power transistor device achieves breakdown voltage greater than 100V at a leakage current density of 1 μamp per mm 2 .
5. The power transistor device of claim 1 , wherein said Group IIIA-N surface layer comprises GaN or AlGaN.
6. The power transistor device of claim 1 , wherein said at least one Group IIIA-N surface layer comprises depositing a Group IIIA-N tri-layer stack including a AlGaN layer sandwiched between a first GaN layer and a second GaN layer, wherein said first GaN layer and said second GaN layer both have a doping concentration between 1×10 15 cm −3 and 1×10 18 cm −3 .
7. The power transistor device of claim 1 , wherein said first voided Group IIIA-N layer and said first essentially void-free Group IIIA-N layer comprise AlN and said first high roughness Group IIIA-N layer and said first essentially smooth Group IIIA-N layer both comprise AlGaN.
8. The power transistor device of claim 1 , wherein said plurality of buffer layers are all essentially crack-free having zero cracks.