Current aperture vertical electron transistors with ammonia molecular beam epitaxy grown p-type gallium nitride as a current blocking layer
A current aperture vertical electron transistor (CAVET) with ammonia (NH 3 ) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.
1. A current aperture vertical electron transistor (CAVET), comprising:
a first III-Nitride layer comprising a current aperture region;
a conductive p-type III-Nitride current blocking layer on sides of the current aperture region;
a semiconductor layer over and contacting both the first III-Nitride layer and the III-Nitride current blocking layer, the semiconductor layer including a conductive channel therein and a source implant region made for a source contact into the semiconductor layer, and wherein the current blocking layer is separated from the source implant region by at least one other region; and
the source contact electrically connected to the conductive channel and to the III-Nitride current blocking layer.
2. The transistor of claim 1 , wherein the III-Nitride current blocking layer is an active p-type layer and p-type dopants for the p-type layer are incorporated into the current blocking layer during growth of the current blocking layer.
3. The transistor of claim 2 , wherein the hole concentration and the composition of the III-Nitride current blocking layer are such that the barrier to the electron flow through the III-Nitride current blocking layer is at least 2 electron volts.
4. The transistor of claim 1 , wherein:
the semiconductor layer includes a GaN layer and an AlGaN barrier layer, and
the conductive channel is in the GaN layer.
5. The transistor of claim 1 , further comprising a drain on an opposite side of the III-Nitride current blocking layer from the source contact, and wherein III-Nitride in the current blocking layer is grown using ammonia assisted molecular beam epitaxy and the current aperture region is grown using Metal Organic Chemical Vapor Deposition.
6. The transistor of claim 1 , wherein:
the III-Nitride current blocking layer surrounds and is all around the current aperture region,
the source contact is electrically connected to the conductive channel and to the III-Nitride current blocking layer, such that during operation of the CAVET, there is no bias between the source contact and the III-Nitride current blocking layer, and
a hole concentration and composition of the III-Nitride current blocking layer cause the barrier to electron flow through the III-Nitride current blocking layer to be at least 1 electron volt.
7. The transistor of claim 1 , wherein a hole concentration and composition of the III-Nitride current blocking layer are such that the III-nitride current blocking layer is sufficiently p-type conductive to achieve high frequency operation characterized by:
the transistor's current-voltage characteristic having no current collapse when pulsed gate voltages (Vgs), having a width of 80 microseconds, are applied from Vgs=0 to −10 V in −2 V step increments.
8. The CAVET of claim 1 , wherein the source contact is deposited in a trench through the semiconductor layer and the source contact in the trench contacts the current blocking layer.
9. The CAVET of claim 1 , wherein:
the CAVET has a drain-source current of less than 0.5 kA/cm 2 for all drain source voltages in a range of 0-10 Volts, at pinch off, for DC operation, and for the gate pulsed with a 80 microsecond pulse width, and
the CAVET's pulsed current voltage characteristic, with the gate pulsed with the 80 microsecond pulse width, is identical to within 5% of the CAVET's direct current (DC) current voltage characteristic, for a drain-source voltage of 2 volts.
10. A current aperture vertical electron transistor (CAVET), comprising:
a first III-Nitride layer comprising a current aperture region;
a conductive p-type III-Nitride current blocking layer on sides of the current aperture region; and
a semiconductor layer over and contacting both the first III-Nitride layer and the III-Nitride current blocking layer, the semiconductor layer including a conductive channel therein and a source implant region made for a source contact into the semiconductor layer, and wherein the current blocking layer is separated from the source implant region by at least one other region; wherein:
a barrier to electron flow through the III-Nitride current blocking layer is at least 1 electron volt.
11. The transistor of claim 10 , wherein a hole concentration of the III-Nitride current blocking layer is such that the CAVET is operable to prevent a current density greater than 0.4 A/cm 2 from flowing through the III-Nitride current blocking layer when the CAVET is biased in an off state with a source-drain voltage of 400V.
12. The transistor of claim 10 , wherein
the III-Nitride current blocking layer is an active p-type layer,
the first III-nitride layer is grown using Metal Organic Chemical Vapor Deposition, and
the semiconductor layer is grown using ammonia assisted molecular beam epitaxy (ammonia-MBE).
13. The transistor of claim 12 , wherein a hole concentration and composition of the III-Nitride current blocking layer cause the barrier to electron flow through the III-Nitride current blocking layer to be at least 1 electron volt.
14. The transistor of claim 12 , wherein a hole concentration and composition of the III-Nitride current blocking layer cause the barrier to electron flow through the III-Nitride current blocking layer to be at least 2 electron volts.
15. The transistor of claim 10 , wherein:
the semiconductor layer includes a GaN layer and an AlGaN barrier layer, and
the conductive channel is in the GaN layer.
16. The transistor of claim 10 , further comprising:
a source contact electrically connected to the conductive channel and to the III-Nitride current blocking layer, such that during operation of the CAVET, there is no bias between the source contact and the III-Nitride current blocking layer, and
a drain on an opposite side of the III-Nitride current blocking layer from the source contact,
wherein III-Nitride in current blocking layer is fabricated under conditions, including temperature and an ambient sufficiently free from hydrogen, to activate p-type dopants in the III-nitride and obtain the current blocking layer that is conductive.
17. The transistor of claim 10 , wherein the III-Nitride current blocking layer surrounds and is all around the current aperture region.
18. A current aperture vertical electron transistor (CAVET), comprising:
a first III-Nitride layer comprising a current aperture region;
a conductive p-type III-Nitride current blocking layer on sides of the current aperture region; and
a semiconductor layer over and contacting both the first III-Nitride layer and the III-Nitride current blocking layer, the semiconductor layer including a conductive channel therein and a source implant region made for a source contact into the semiconductor layer, and wherein the current blocking layer is separated from the source implant region by at least one other region; wherein:
a composition of the III-Nitride current blocking layer is such that the CAVET is operable to prevent a current density greater than 0.4 A/cm 2 from flowing through the III-Nitride current blocking layer when the CAVET is biased in an off state with a source-drain voltage of 400V.
19. The transistor of claim 18 , wherein;
the III-Nitride current blocking layer is an active p-type layer,
p-type dopants for the p-type layer are incorporated into the current blocking layer during growth of the current blocking layer, and
subsequent growth of the semiconductor layer is under conditions that reduce passivation of the p-type dopants, and
such that the p-type layer has a p-type doping level of at least 5×10 19 cm −3 .
20. The transistor of claim 19 , wherein a hole concentration and composition of the III-Nitride current blocking layer cause the barrier to electron flow through the III-Nitride current blocking layer to be at least 1 electron volt.
21. The transistor of claim 19 , wherein a hole concentration and composition of the III-Nitride current blocking layer cause the barrier to electron flow through the III-Nitride current blocking layer to be at least 2 electron volts.
22. The transistor of claim 18 , wherein:
the semiconductor layer includes a GaN layer and an AlGaN barrier layer, and
the conductive channel is in the GaN layer.
23. A method of fabricating a current aperture vertical electron transistor (CAVET), comprising:
forming a first III-Nitride layer comprising a current aperture region, wherein the first III-nitride layer is grown using Metal Organic Chemical Vapor Deposition;
forming a conductive III-Nitride current blocking layer on sides of the current aperture region, wherein III-nitride in the current blocking layer is grown using ammonia assisted molecular beam epitaxy (ammonia-MBE) under conditions that reduce passivation of p-type dopants in the current blocking layer;
planarizing a surface of the current aperture region;
growing a semiconductor layer, over and cantacting both the first III- Nitride layer and the III-Nitride current blocking layer, using ammonia-MBE, the semiconductor layer including a conductive channel therein;
forming a trench through the semiconductor layer to the current blocking layer; and
depositing a source contact into the trench to contact the current blocking layer.