FinFET with multiple dislocation planes and method for forming the same

1. A method comprising:

forming a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first trench;

forming a first structurally amorphous region in the substrate and between the first semiconductor fin and the second semiconductor fin;

forming a first dislocation plane by applying a first anneal process to the first structurally amorphous region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin;

applying an etching process to the first semiconductor fin to form a first drain/source recess;

forming a second structurally amorphous region underlying the first drain/source recess; and

forming a second dislocation plane by applying a second anneal process to the second structurally amorphous region, wherein the first dislocation plane is orthogonal to the second dislocation plane.

2. The method of claim 1 , further comprising:

applying a pre-amorphous implantation process to the substrate to form the first structurally amorphous region.

3. The method of claim 1 , further comprising:

prior to the step of forming the first dislocation plane, depositing a first buffer oxide layer over a bottom and sidewalls of the first trench; and

depositing a first tensile film layer over the first buffer oxide layer.

4. The method of claim 1 , further comprising:

forming a first drain/source region in the first drain/source recess, wherein the second dislocation plane is underlying the first drain/source region.

5. The method of claim 1 , further comprising:

prior to the step of forming the second dislocation plane, depositing a second buffer oxide layer over a bottom and sidewalls of the first drain/source recess; and

depositing a second tensile film layer over the second buffer oxide layer.

6. The method of claim 1 , further comprising:

forming an isolation region in the first trench; and

recessing the isolation region so that the first semiconductor fin and the second semiconductor fin protrude over a top surface of the isolation region.

7. The method of claim 6 , wherein:

the isolation region is a shallow trench isolation region.

8. A method comprising:

forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench;

applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process;

depositing a first oxide layer on sidewalls and a bottom of the trench;

depositing a first tensile film layer over the first oxide layer;

converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process, wherein the first dislocation plane extends in a first direction; and

forming a second dislocation plane underlying a first drain/source region, wherein the second dislocation plane extends in a second direction orthogonal to the first direction.

9. The method of claim 8 , further comprising:

forming a first drain/source recess;

depositing a second oxide layer on sidewalls and a bottom of the first drain/source recess;

depositing a second tensile film layer over the second oxide layer; and

applying a second PAI process to the substrate and forming a second PAI region underlying the first drain/source recess as a result of the second PAI process.

10. The method of claim 9 , further comprising:

converting the second PAI region into the second dislocation plane using a second anneal process.

11. The method of claim 9 , further comprising:

forming a first drain/source region in the first drain/source recess;

forming a second drain/source region in a second drain/source recess; and

forming a gate structure wrapping a channel region around three sides.

12. The method of claim 11 , wherein:

the first drain/source region, the second drain/source region and the gate structure form an n-type fin field-effect-transistor.

13. The method of claim 8 , further comprising:

forming a third fin over the substrate, wherein the third fin and the second fin are separated by a second isolation region; and

forming a third dislocation plane underlying the second isolation region.

14. The method of claim 13 , wherein:

the first dislocation plane and the third dislocation plane are parallel to each other.

15. A method comprising:

forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench;

applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process;

depositing a first tensile film layer on sidewalls and a bottom of the trench;

converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process; and

forming an isolation region over the first dislocation plane.

16. The method of claim 15 , further comprising:

removing a portion of the first fin to form a drain/source trench;

applying a second PAI process to the substrate and forming a second PAI region underlying the drain/source trench as a result of the second PAI process;

depositing a second tensile film layer on sidewalls and a bottom of the drain/source trench; and

converting the second PAI region into a second dislocation plane underlying the drain/source trench using a second anneal process.

17. The method of claim 16 , further comprising:

performing an epitaxial growth process to from a drain/source region in the drain/source trench.

18. The method of claim 16 , further comprising:

the second dislocation plane is orthogonal to the first dislocation plane.

19. The method of claim 15 , wherein:

the first anneal process is of a temperature in a range from about 500 degrees to about 700 degrees.

20. The method of claim 15 , further comprising:

forming an isolation region in the trench.