IP Library Granted Patent US 9,595,533
Granted Patent B2
US 9,595,533 · App. 13/599,793 · Granted Mar 14, 2017

Memory array having connections going through control gates

Inventors: Toru Tanzawa (Tokyo, JP); Tamotsu Murakoshi (Kanagawa, JP); Deepak Thimmegowda (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11582G11C16/0483H01L27/11529H01L27/11548H01L27/11556H01L27/11573H01L27/11575H01L29/66833H01L29/7926
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Quick Facts
Patent No.
US 9,595,533
App. No.
13/599,793
Granted
Mar 14, 2017
Kind
B2
Abstract

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Claims (26)

1. An apparatus comprising:

a substrate;

a memory cell string including a body and memory cells located in different levels of the apparatus;

a first conductive material over the substrate, the first conductive material being part of a select gate associated with the memory cell string and including a portion opposing a first portion of the body;

a second conductive material over the substrate, the second conductive material being part of a control gate associated with the memory cell string and including a portion opposing a second portion of the body;

a first connection coupled to a first contact area of the first conductive material and to a first conductive contact located between the first conductive material and the substrate, the first connection including a portion going through a portion of the control gate, wherein no portion of the first connection is going through the select gate; and

a second connection coupled to a second contact area of the second conductive material and to a second conductive contact located between the second conductive material and the substrate, wherein the second connection includes a segment between the first and second contact areas and extending from one level to another level of the apparatus.

2. The apparatus of claim 1 , wherein the second connection includes a first segment perpendicular to the substrate, a second segment perpendicular to the substrate, and a third segment coupling the first segment to the second segment, the third segment being parallel to the substrate and extending between the first and second contact areas.

3. The apparatus of claim 2 , wherein the second segment of the second connection includes the segment between the first and second contact areas.

4. The apparatus of claim 1 , wherein the apparatus comprises a memory device, the memory device comprising the memory cell string.

5. An apparatus comprising:

a substrate;

a memory cell string including a body;

a select gate located in a first level of the apparatus and along a first portion of the body;

a control gate located in a second level of the apparatus and along a second portion of the body;

a first connection coupled to the select gate and to a first transistor having at least a portion formed in the substrate, the first connection including a portion going through a portion of the control gate, wherein no portion of the first connection is going through the select gate; and

a second connection coupled to the control gate and to a second transistor having at least a portion formed in the substrate, wherein the first and second connections are on a same side of the body of the memory cell string.

6. The apparatus of claim 5 , further comprising an opening through the control gate, wherein the portion of the first connection going through the portion of the control gate is inside the opening.

7. The apparatus of claim 6 , further comprising:

an additional memory cell string including an additional body extending outwardly from the substrate;

an additional select gate located in the first level of the apparatus and along a portion of the additional body; and

an additional connection coupled to the additional select gate and to an additional transistor having at least a portion formed in the substrate, the additional connection including a portion going through an additional opening in the control gate.

8. The apparatus of claim 5 , further comprising an additional control gate located in a third level of the apparatus and along a third portion of the body, wherein the first connection includes an additional portion going through a portion of the additional control gate.

9. The apparatus of claim 8 , further comprising an opening through the control gate and the additional control gate, wherein the portion of the first connection going through the portion of the control gate is inside the opening, and the additional portion of the first connection going through the portion of the additional control gate is also inside the opening.

10. The apparatus of claim 9 , wherein the select gate includes an edge, the control gate includes an edge, and the opening is between the edge of the select gate and the edge of the control gate.

11. The apparatus of claim 10 , wherein the distance between the body and the edge of the control gate is greater than a distance between the body and the edge of the select gate.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064988/0210 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2013
From: TANZAWA, TORU; MURAKOSHI, TAMOTSU; THIMMEGOWDA, DEEPAK
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030784/0209 →
Continuity (1)
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