Memory power management and data consolidation
According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.
1. A system for memory power management comprising:
a plurality of real memory portions including a first real memory portion and a second real memory portion, wherein each of the plurality of real memory portions has a dedicated buffer and is a rank of memory located on a dual inline memory module (DIMM) that provides a physical location for data to be stored, including a first dedicated buffer connected to the first real memory portion and a second dedicated buffer connected to the second real memory portion, wherein each of the dedicated buffers is configured to verify channel connectivity, synchronize the DIMMs, and detect errors;
a migration bus, the migration bus connecting each of the dedicated buffers;
a data management controller, within at least one of the dedicated buffers, the data management controller configured to
migrate data, from the first real memory portion to the second real memory portion across the migration bus through the first and second dedicated buffers, and
place the first real memory portion into a reduced power mode; and
a memory controller, wherein the plurality of real memory portions is coupled to the memory controller by a memory bus, wherein the memory controller is configured to select the first and second real memory portions, wherein the data management controller is configured to migrate data from the selected first real memory portion to the selected second real memory portion.
2. The system of claim 1 , wherein the migration bus connects each of the dedicated buffers in a daisy chain.
3. The system of claim 1 , wherein the plurality of real memory portions includes a third real memory portion connected to a third dedicated buffer, the data management controller configured to migrate data, from the first real memory portion to at least the second and third real memory portions across the migration bus through the first, second, and third dedicated buffers.
4. The system of claim 1 , further comprising a hardware controller, the hardware controller including a physical address of the data, the data management controller further configured to update the physical address of the data from the first real memory portion to the second real memory portion.
5. The system of claim 4 , wherein the hardware controller includes a hypervisor.
6. The system of claim 1 , wherein the memory controller is further configured to
select the first and second real memory portions in response to a migration trigger, the migration trigger including determining that the first real memory portion stores data having a data size less than an available capacity of the second real memory portion.
7. The system of claim 1 , wherein the memory controller is further configured to
select the first and second real memory portions based on a migration trigger, the migration trigger including determining that the data in the first real memory portion is below a transfer threshold.
8. The system of claim 1 , wherein the memory controller is further configured to
select the first and second real memory portions based on a migration trigger, the migration trigger including determining that the second real memory portion has an available capacity to receive the data from the first real memory portion.
9. The system of claim 1 , wherein the memory controller is further configured to
select the first and second real memory portions based on a migration trigger, the migration trigger including determining that a first power consumption value for the first real memory portion is greater than a second power consumption value for the second real memory portion.