Detecting defective connections in stacked memory devices
A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
1. A stacked memory device comprising:
a plurality of memory chips each having a plurality of memory locations, a plurality of bit lines and a plurality of word lines; and,
a logic chip having electrical connections to, and located beneath, each of the plurality of memory chips, and designed to:
write a write data value into a location of the plurality of memory locations in a memory chip of the plurality of memory chips;
read a read data value from the location in the memory chip;
detect a bit error in the read data value;
record a bit number corresponding to a detected bit error; and,
replace a defective connection between at least one of the plurality of memory chips and the logic chip, with a spare connection.
2. The stacked memory device of claim 1 , wherein the electrical connections are through-silicon vias (TSVs).
3. The stacked memory device of claim 1 , wherein the logic chip is a member of a group consisting of: a processor chip, a memory controller chip and a memory buffer chip.
4. The stacked memory device of claim 1 , wherein a multiplexer is configured to replace the defective connection with a spare connection.