IP Library Granted Patent US 9,613,826
Granted Patent B2
US 9,613,826 · App. 14/811,852 · Granted Apr 4, 2017

Semiconductor process for treating metal gate

Inventors: Cheng-Chi Tai (Taichung, TW); Chun-Ju Tao (Yunlin County, TW); Chung-Che Huang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/32136H01L21/283H01L21/31144H01L21/76897H01L29/45H01L29/495H01L29/517H01L29/66477
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Quick Facts
Patent No.
US 9,613,826
App. No.
14/811,852
Granted
Apr 4, 2017
Kind
B2
Abstract

A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H 2 /N 2 plasma treatment process is performed to reduce the main conductive material.

Claims (22)

1. A semiconductor process for treating a metal gate, comprising:

providing a metal gate comprising a main conductive material on a substrate;

performing a H2/N2 plasma treatment process to deoxidize the main conductive material; and

forming a contact plug contacting the main conductive material after the H2/N2 plasma treatment process is performed.

2. The semiconductor process for treating a metal gate according to claim 1 , wherein the main conductive material comprises a metal oxide layer at a top surface of a metal layer.

3. The semiconductor process for treating a metal gate according to claim 2 , wherein the metal oxide layer is reduced into a part of the metal layer while the H2/N2 plasma treatment process is performed.

4. The semiconductor process for treating a metal gate according to claim 3 , wherein the main conductive material comprises aluminum or tungsten.

5. The semiconductor process for treating a metal gate according to claim 4 , wherein the metal oxide layer comprises an aluminum oxide layer while the metal layer comprises an aluminum layer.

6. The semiconductor process for treating a metal gate according to claim 1 , wherein the H2/N2 plasma treatment process comprises supplying a gas mixture of H2/N2 with a ratio of 2-3.5%.

7. The semiconductor process for treating a metal gate according to claim 6 , wherein the H2/N2 plasma treatment process comprises supplying a gas mixture of H2/N2 with a ratio of 2.9%.

8. The semiconductor process for treating a metal gate according to claim 1 , wherein the H2/N2 plasma treatment process comprises inserting an N2 gas while supplying a gas mixture of H2/N2.

9. The semiconductor process for treating a metal gate according to claim 8 , wherein the H2/N2 plasma treatment process comprises inserting an N2 gas of 1900 sccm while supplying a gas mixture of H2/N2 with a ratio of 4% of 5000 sccm.

10. The semiconductor process for treating a metal gate according to claim 1 , further comprising:

forming a dielectric layer on the metal gate and patterning the dielectric layer to expose the main conductive material by using a photoresist layer and then removing the photoresist layer before the H2/N2 plasma treatment process is performed.

11. The semiconductor process for treating a metal gate according to claim 10 , further comprising:

performing a strip treatment process to remove the photoresist layer before the H2/N2 plasma treatment process is performed.

12. The semiconductor process for treating a metal gate according to claim 11 , wherein the strip treatment process comprises an O2 strip treatment process.

13. The semiconductor process for treating a metal gate according to claim 11 , wherein the strip treatment process comprises a first H2/N2 plasma treatment process having higher H2/N2 ratio than the H2/N2 plasma treatment process.

14. The semiconductor process for treating a metal gate according to claim 13 , wherein the first H2/N2 plasma treatment process has a H2/N2 ratio of 4%.

15. The semiconductor process for treating a metal gate according to claim 1 , further comprising:

forming a source/drain in the substrate beside the metal gate; and

forming S/D contact plugs directly contacting the source/drain while the contact plug contacting the main conductive material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2015
From: TAI, CHENG-CHI; TAO, CHUN-JU; HUANG, CHUNG-CHE
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036201/0097 →
Continuity (1)
Related Publication 20170032975A1 · Feb 2, 2017