Embedded transistor
View Patent ↗An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.
1. A device comprising:
a substrate;
a first recess and a second recess in the substrate, the first recess having a first bottom and the second recess having a second bottom, the first bottom and the second bottom being at a same first depth;
a dielectric material filling the first recess;
a gate dielectric along sidewalls and a bottom of the second recess;
a gate electrode over the gate dielectric, the gate electrode having a top surface below an uppermost surface of the substrate; and
source/drain regions in the substrate on opposing sides of the second recess.
2. The device of claim 1 , further comprising a storage node electrically coupled to one of the source/drain regions.
3. The device of claim 2 , wherein the storage node comprises a metal-insulator-metal (MIM) capacitor.
4. The device of claim 2 , further comprising a bit line electrically coupled to one of the source/drain regions.
5. The device of claim 1 , wherein the gate electrode is electrically coupled to a word line.
6. The device of claim 1 , wherein a width of the first recess is different than a width of the second recess.
7. The device of claim 1 , wherein the first same depth is between about 1,000 Å and about 4,000 Å.
8. A device comprising:
a substrate;
a shallow trench isolation in the substrate, the shallow trench isolation being filled with a dielectric material;
a recess in the substrate, a bottom of the recess having a same depth as a bottom of the shallow trench isolation;
a gate dielectric along a bottom and sidewalls of the recess;
a gate electrode over the gate dielectric, the gate dielectric completely separating the gate electrode from the substrate;
a dielectric layer over the gate electrode, the dielectric layer extending into the recess; and
source/drain regions in the substrate on opposing sides of the recess.
9. The device of claim 8 , wherein the gate dielectric extends to an uppermost surface of the substrate.
10. The device of claim 8 , wherein an uppermost surface of the dielectric layer is coplanar with an uppermost surface of the shallow trench isolation.
11. The device of claim 8 , wherein the shallow trench isolation has a first width and the recess has a second width, the first width being different than the second width.
12. The device of claim 8 , wherein the gate dielectric has a different thickness along a bottom than along sidewalls of the recess.
13. The device of claim 8 , further comprising a metal-insulator-metal (MIM) capacitor coupled directly to one of the source/drain regions.
14. The device of claim 13 , further comprising a bit line electrically coupled to another one of the source/drain regions.
15. The device of claim 14 , wherein the gate electrode is electrically coupled to a word line.
16. A device comprising:
a substrate;
a shallow trench isolation in the substrate, the shallow trench isolation being completely filled with dielectric material;
a first recess in the substrate, a depth of a bottom of the first recess having a same depth as a bottom of the shallow trench isolation;
a gate dielectric along a bottom and sidewalls of the first recess;
a gate electrode over the gate dielectric;
a first source/drain region along a surface of the substrate on a first side of the first recess;
a second source/drain region along the surface of the substrate on a second side of the first recess;
a first contact electrically coupled between the first source/drain region and a bit line; and
a second contact electrically coupled between the second source/drain region and a storage node, wherein the first contact and the second contact are laterally offset along a longitudinal access axis of the first recess.
17. The device of claim 16 , further comprising a second recess in the substrate, wherein the shallow trench isolation is interposed between the first recess and the second recess.
18. The device of claim 16 , further comprising a dielectric layer over the gate electrode, an uppermost surface of the dielectric layer being coplanar with an uppermost surface of the substrate.
19. The device of claim 16 , wherein the shallow trench isolation has a first width and the first recess has a second width, the first width being different than the second width.
20. The device of claim 16 , wherein the gate dielectric has a first thickness along a bottom of the first recess and a second thickness along a sidewall of the first recess, wherein the first thickness is different than the second thickness.