IP Library › Granted Patent US 9,614,143
Granted Patent B2
US 9,614,143 · App. 14/735,006 · Granted Apr 4, 2017

De-integrated trench formation for advanced MRAM integration

Inventors: Yu Lu (San Diego, CA); Wei-Chuan Chen (Taipei, TW); Seung Hyuk Kang (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H01L43/02H01L27/222H01L43/08H01L43/10H01L43/12
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Quick Facts
Patent No.
US 9,614,143
App. No.
14/735,006
Granted
Apr 4, 2017
Kind
B2
Abstract

A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

Claims (16)

1. A semiconductor device including a magnetic tunnel junction (MTJ) region and a logic region adjacent to the MTJ region, the device comprising:

a magnetoresistive random-access memory (MRAM) trench within the MTJ region of the semiconductor device, the MRAM trench comprising a first conductive barrier liner and a second conductive barrier liner, the MRAM trench having a flat portion landing no deeper than an adjoining surface of a hard mask and an encapsulation layer of an MTJ within the MTJ region of the semiconductor device, in which the second conductive barrier liner is on sidewalls and a surface of the MRAM trench, and the first conductive barrier liner is on the second conductive barrier liner;

a logic trench comprising the first conductive barrier liner; and

a logic via comprising the first conductive barrier liner, the logic via landing on a first portion of a conductive interconnect (Mx) within the logic region of the semiconductor device.

2. The semiconductor device of claim 1 , further comprising an edge via and an edge trench comprising the first conductive barrier liner and the second conductive barrier liner, the edge via landing on a bottom electrode contact of a bottom electrode coupled to a second portion of the conductive interconnect (Mx).

3. The semiconductor device of claim 1 in which the first conductive barrier liner comprises ruthenium (Ru), cobalt (Co), and/or manganese (Mn).

4. The semiconductor device of claim 1 further comprising a capping layer on the MRAM trench and the logic trench.

5. The semiconductor device of claim 1 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

6. A semiconductor device including a magnetic tunnel junction (MTJ) region and a logic region adjacent to the MTJ region, the device comprising:

a magnetoresistive random-access memory (MRAM) trench within the MTJ region of the semiconductor device, the MRAM trench comprising a first conductive barrier liner and a second conductive barrier liner, the MRAM trench having a flat portion landing no deeper than an adjoining surface of a hard mask and an encapsulation layer of an MTJ within the MTJ region of the semiconductor device, in which the second conductive barrier liner is on sidewalls and a surface of the MRAM trench, and the first conductive barrier liner is on the second conductive barrier liner;

a logic trench comprising the first conductive barrier liner; and

a logic via comprising the first conductive barrier liner, the logic via landing on a first portion of a means for interconnecting within the logic region of the semiconductor device.

7. The semiconductor device of claim 6 , further comprising an edge via and an edge trench comprising the first conductive barrier liner and the second conductive barrier liner, the edge via landing on a bottom electrode contact of a bottom electrode coupled to a second portion of the interconnecting means.

8. The semiconductor device of claim 6 in which the first conductive barrier liner comprises ruthenium (Ru), cobalt (Co), and/or manganese (Mn).

9. The semiconductor device of claim 6 further comprising a capping layer on the MRAM trench and the logic trench.

10. The semiconductor device of claim 6 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2015
From: LU, YU; CHEN, WEI-CHUAN; KANG, SEUNG HYUK
To: QUALCOMM INCORPORATED
Reel/Frame 036143/0112 →
Continuity (1)
Related Publication 20160365505A1 · Dec 15, 2016