Method and apparatus to increase efficiency in a power factor correction circuit

1. A power factor correction (PFC) controller, comprising:

a driver circuit coupled to vary the switching frequency of the power switch of the PFC converter in response to an input current of a PFC converter and an input voltage of the PFC converter and to output a third signal to switch the power switch of the PFC converter to control the input current to substantially follow the input voltage; and

a frequency adjust circuit coupled to receive an error voltage signal representative of an output of the PFC converter, wherein the frequency adjust circuit is further coupled to output an adjusted error signal to adjust the end of the off time of the power switch of the PFC converter in response to the error voltage signal;

a first integrator coupled to integrate an input current of a PFC converter, wherein a first signal is generated in response to the first integrator to end an on time of a power switch of the PFC converter; and

a second integrator coupled to integrate a difference between a constant voltage and an input voltage of the PFC converter, wherein a second signal is generated in response to the second integrator to end an off time of the power switch of the PFC converter; wherein the driver circuit is coupled to vary the switching frequency of the power switch of the PFC converter in response to the first signal and the second signal.

2. The PFC controller of claim 1 wherein the driver circuit is coupled to regulate an output voltage of the PFC converter.

3. The PFC controller of claim 1 wherein the power switch of the PFC converter comprises a metal oxide field effect transistor (MOSFET).

4. The PFC controller of claim 1 further comprising an error amplifier coupled to generate the error voltage signal in response to a feedback signal representative of the output of the PFC converter and a reference voltage.

5. The PFC controller of claim 1 wherein the first integrator includes a first capacitor coupled to be charged with a scaled current when the power switch is on, wherein the scaled current is representative of the input current.

6. The PFC controller of claim 5 wherein a scaling factor of the scaled current is representative of a peak input voltage of the input voltage in a half-line cycle.

7. The PFC controller of claim 5 wherein a scaling factor of the scaled current is representative of an rms value of the input voltage.

8. The PFC controller of claim 5 wherein a scaling factor of the scaled current is representative of an average input voltage over a half cycle.

9. The PFC controller of claim 5 further comprising a first comparator coupled to compare a voltage on the first capacitor with the error voltage signal representative of an output of the PFC converter and to generate the first signal.

10. The PFC controller of claim 1 wherein the second integrator includes a second capacitor coupled to be charged with a difference between a scaled current and a reference current when the power switch is off, wherein the scaled current is representative of the input voltage.

11. The PFC controller of claim 10 wherein a scaling factor of the scaled current is representative of an instantaneous dc input voltage.

12. The PFC controller of claim 10 further comprising a second comparator coupled to compare a voltage on the second capacitor with an adjusted error signal and to generate the second signal.