IP Library › Granted Patent US 9,619,416
Granted Patent B2
US 9,619,416 · App. 14/667,997 · Granted Apr 11, 2017

Inter-component communication including posted and non-posted transactions

Inventors: Mikal C. Hunsaker (El Dorado Hills, CA); Su Wei Lim (Klang, MY); Ricardo E. James (San Jose, CA)
Assignee: Intel Corporation
G06F13/364G06F1/06G06F1/24G06F11/0727G06F11/1004G06F11/221G06F11/2289G06F11/3027G06F13/00G06F13/122G06F13/1668G06F13/4068G06F13/423G06F13/4221G06F13/4234G06F13/4291
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Quick Facts
Patent No.
US 9,619,416
App. No.
14/667,997
Granted
Apr 11, 2017
Kind
B2
Abstract

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Claims (88)

1. An apparatus comprising:

a clock (CLK) pin;

a plurality of input/output (I/O) pins [n:0];

a chip select pin;

an Alert pin; and

a logic unit to cause a slave initiated posted or non-posted transaction, wherein

the slave initiated posted transaction comprises transmission of an alert signal using the Alert pin and includes transmission of a response code using at least one of the I/O pins in response to receipt of a Get_Status command and a cyclic redundancy check (CRC) value on at least one of the I/O pins and

the slave initiated non-posted transaction comprises transmission of an alert signal using the Alert pin and includes transmission of a response code using at least one of the I/O pins in response to receipt of a Get_Status command and a CRC value on at least one of the I/O pins.

2. The apparatus of claim 1 , wherein the slave initiated posted transaction comprises:

receipt of a GET_PC command and a second CRC value and

transmission of an ACCEPT response code and one or more of: a status (STS), a header (HDR), data, or a CRC value.

3. The apparatus of claim 1 , wherein the slave initiated non-posted transaction comprises:

receipt of a Get_NP command and a second CRC value, in response to receipt of the Get_NP command, transmission of an ACCEPT response code and one or more of a status (STS), a header (HDR), or a CRC value,

receipt of a PUT_PC command and one or more of: data, an HDR, or a CRC value, and

in response to receipt of the PUT_PC command, transmission of an ACCEPT response code and one or more of: an STS or a CRC value.

4. The apparatus of claim 1 , further comprising a status register.

5. The apparatus of claim 1 , wherein the Alert pin comprises an Alert# pin.

6. The apparatus of claim 1 , further comprising at least one of:

a virtual wire controller, a tunneled SMBus controller, a Flash controller, a touch screen, or a camera.

7. The apparatus of claim 2 , wherein

the GET_PC command comprises a request to get a posted or completion header and optional data.

8. The apparatus of claim 3 , wherein

the Get_NP command comprises a request to get a non-posted header and optional data and

the PUT_PC command comprises a request to put a posted or completion header and optional data.

9. The apparatus of claim 6 , further comprising:

a host bridge;

a flash device controller; and

a host central processing unit, the host bridge communicatively coupled to the flash device controller, the host central processing unit, and the logic unit.

10. The apparatus of claim 9 , further comprising:

telephone circuitry and

a display.

11. A method comprising:

receiving a clock signal at a clock (CLK) pin and

causing a slave initiated posted or non-posted transaction, wherein

the slave initiated posted transaction comprises transmitting an alert signal using an Alert pin and includes transmitting a response code using at least one I/O pin in response to receipt of a Get_Status command and a cyclic redundancy check (CRC) value on at least one I/O pin and

the slave initiated non-posted transaction comprises transmitting an alert signal using an Alert pin and includes transmitting a response code using at least one I/O pin in response to receipt of a Get_Status command and a CRC value on at least one I/O pin.

12. The method of claim 11 , wherein the slave initiated posted transaction comprises:

receiving a GET_PC command and a second CRC value and

transmitting an ACCEPT response code and one or more of: a status (STS), a header (HDR), data, or a CRC value.

13. The method of claim 11 , wherein the slave initiated non-posted transaction comprises:

receiving a Get_NP command and a second CRC value,

in response to receipt of the Get_NP command, transmitting an ACCEPT response code and one or more of a status (STS), a header (HDR), or a CRC value,

receiving a PUT_PC command and one or more of: data, an HDR, or a CRC value, and

in response to receipt of the PUT_PC command, transmitting an ACCEPT response code and one or more of: an STS or a CRC value.

14. The method of claim 11 , wherein the Alert pin comprises an Alert# pin.

15. The method of claim 12 , wherein

the GET_PC command comprises a request to get a posted or completion header and optional data.

16. The method of claim 13 , wherein

the Get_NP command comprises a request to get a non-posted header and optional data and

the PUT_PC command comprises a request to put a posted or completion header and optional data.

17. An apparatus comprising:

a clock (CLK) pin to provide a clock signal;

a plurality of input/output (I/O) pins [n:0];

an Alert pin; and

a logic unit to receive a slave initiated posted or non-posted transaction, wherein

the slave initiated posted transaction comprises receipt of an alert signal using the Alert pin, transmission of a Get_Status command and a cyclic redundancy check (CRC) value using at least one of the I/O pins, and receipt of a response code using at least one of the I/O pins and

the slave initiated non-posted transaction comprises receipt of an alert signal using the Alert pin, transmission of a Get_Status command and a CRC value on at least one of the I/O pins, and receipt of a response code on at least one of the I/O pins.

18. The apparatus of claim 17 , wherein the slave initiated posted transaction comprises:

transmission of a GET_PC command and a second CRC value and

receipt of an ACCEPT response code and one or more of: a status (STS), a header (HDR), data, or a CRC value.

19. The apparatus of claim 18 , wherein:

the GET_PC command comprises a request to get a posted or completion header and optional data.

20. The apparatus of claim 17 , wherein the slave initiated non-posted transaction comprises:

transmission of a Get_NP command and a CRC value, in response to transmission of the Get_NP command, receipt of an ACCEPT response code and one or more of a status (STS), a header (HDR), or a CRC value,

transmission of a PUT_PC command and one or more of: data, an HDR, or a CRC value, and

in response to transmission of the PUT_PC command, receipt of an ACCEPT response code and one or more of: an STS or a CRC value.

21. The apparatus of claim 17 , wherein the Alert pin comprises an Alert# pin.

22. The apparatus of claim 20 , wherein

the Get_NP command comprises a request to get a non-posted header and optional data and

the PUT_PC command comprises a request to put a posted or completion header and optional data.

23. A method comprising:

transmitting a clock signal from a clock (CLK) pin and

receiving a slave initiated posted or non-posted transaction, wherein

the slave initiated posted transaction comprises: receiving an alert signal on an Alert pin, transmitting a Get_Status command and a cyclic redundancy check (CRC) value from at least one I/O pin, and receiving a response code on at least one I/O pin and

the slave initiated non-posted transaction comprises: receiving an alert signal on an Alert pin, transmitting a Get_Status command and a CRC value from at least one I/O pin, and receiving a response code on at least one I/O pin.

24. The method of claim 23 , wherein the slave initiated posted transaction comprises:

transmitting a GET_PC command and a second CRC value and

receiving an ACCEPT response code and one or more of: a status (STS), a header (HDR), data, or a CRC value.

25. The method of claim 23 , wherein the slave initiated non-posted transaction comprises:

transmitting a Get_NP command and a CRC value, receiving an ACCEPT response code and one or more of a status (STS), a header (HDR), or a CRC value,

transmitting a PUT_PC command and one or more of: data, an HDR, or a CRC value, and

receiving an ACCEPT response code and one or more of: an STS or a CRC value.

26. The method of claim 23 , wherein the Alert pin comprises an Alert# pin.

27. The method of claim 24 , wherein

the GET_PC command comprises a request to get a posted or completion header and optional data.

28. The method of claim 25 , wherein

the Get_NP command comprises a request to get a non-posted header and optional data and

the PUT_PC command comprises a request to put a posted or completion header and optional data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: HUNSAKER, MIKAL C.; LIM, SU WEI; JAMES, RICARDO E.
To: INTEL CORPORATION
Reel/Frame 041347/0106 →
Continuity (4)
Continuation 14537859 · Nov 10, 2014
Continuation 13436697 · Mar 30, 2012
Provisional Application 61596958 · Feb 9, 2012
Related Publication 20150199296A1 · Jul 16, 2015