Semiconductor device

1. A semiconductor device comprising:

a semiconductor layer made of a wide bandgap semiconductor having a gate trench provided with a sidewall and a bottom wall;

a gate insulating film formed on the sidewall and the bottom wall of the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film,

wherein the semiconductor layer includes:

a source region of a first conductivity type formed to be exposed on the side of a front surface of the semiconductor layer for partially forming the sidewall of the gate trench,

a body region of a second conductivity type formed on a side of the source region closer to a rear surface of the semiconductor layer to be in contact with the source region for partially forming the sidewall of the gate trench,

a drift region of the first conductivity type formed on a side of the body region closer to the rear surface of the semiconductor layer to be in contact with the body region for forming the bottom wall of the gate trench, and

a first breakdown voltage holding region of the second conductivity type selectively formed on an edge portion of the gate trench where the sidewall and the bottom wall intersect with each other in a partial region of the gate trench; wherein the drift region includes:

a first region of a first impurity concentration forming the bottom wall of the gate trench, and

a second region of a second impurity concentration smaller than the first impurity concentration formed on a side of the first region closer to the rear surface of the semiconductor layer to be in contact with the first region; and wherein the semiconductor layer further includes

a source trench having a sidewall and a bottom wall, passing through the source region and the body region from the front surface and reaching the drift region, and

a second breakdown voltage holding region of the second conductivity type selectively formed on an edge portion of the source trench where the sidewall and the bottom wall intersect with each other in a partial region of the source trench.

2. The semiconductor device according to claim 1 , wherein

the impurity concentration in the first breakdown voltage holding region is higher than the impurity concentration in the drift region.

3. The semiconductor device according to claim 1 , wherein

the gate trench is formed in a latticed manner,

the semiconductor layer includes a plurality of unit cells partitioned by the latticed gate trench and provided in the form of polygonal prisms each having a plurality of corner portions, and each unit cell has the source region, the body region and the drift region, and

the first breakdown voltage holding region is selectively formed on a corner edge portion of the gate trench formed on the corner portion of the unit cell.

4. The semiconductor device according to claim 3 , wherein

the first breakdown voltage holding region is formed to reach a portion of the body region immediately above the corner edge portion.

5. The semiconductor device according to claim 3 , wherein

the first breakdown voltage holding region is selectively formed on an intersection portion of the latticed gate trench.

6. The semiconductor device according to claim 3 , wherein the semiconductor layer further includes a third breakdown voltage holding region of the second conductivity type, formed on a bottom wall of a linear portion of the latticed gate trench, having a width narrower than the width of the linear portion.

7. The semiconductor device according to claim 6 , wherein the impurity concentration in the third breakdown voltage holding region is higher than the impurity concentration in the first breakdown voltage holding region.

8. The semiconductor device according to claim 6 , wherein the thickness of the third breakdown voltage holding region is smaller than the thickness of the first breakdown voltage holding region.

9. The semiconductor device according to claim 1 , wherein

the thickness of the first region is greater than the thickness of the first breakdown voltage holding region.

10. The semiconductor device according to claim 1 , wherein the thickness of the first region is not more than the thickness of the first breakdown voltage holding region.

11. The semiconductor device according to claim 1 , wherein the interface between the first region and the second region undulates in response to a step caused by partial lowering of the front surface of the semiconductor layer resulting from the formation of the gate trench.

12. The semiconductor device according to claim 1 , wherein the interface between the first region and the second region is at a constant distance from the front surface of the semiconductor layer.

13. The semiconductor device according to claim 1 , wherein

a portion of the gate insulating film on the bottom wall of the gate trench is thicker than a portion of the gate insulating film on the sidewall of the gate trench, and a top portion thereof is below the deepest portion of the body region.

14. The semiconductor device according to claim 1 , wherein the front surface of the semiconductor layer is a C plane.

15. The semiconductor device according to claim 1 , wherein the body region is formed by ion implantation.