Memory cells formed with sealing material
Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.
1. An array of memory cells, comprising:
a first stack of materials formed on a first conductive material;
first trenches in the first stack formed through the first stack in a first direction, wherein the first trenches comprise:
a plurality of initial trenches in the first direction formed through a first portion of the first stack;
a sealing material formed on sidewalls of the plurality of initial trenches; and
a plurality of completed trenches in the first direction formed through a remaining portion of the first stack and the first conductive material, wherein:
at least a partial depth of the completed trenches has exposed sidewalls without the sealing material thereon; and
a second stack of materials formed on the first stack and comprising:
second trenches formed through the second stack and at least a first portion of the first stack in a second direction, wherein the second trenches comprise a sealing material formed on sidewalls of the second trenches in the second direction.
2. The array of claim 1 , further comprising:
a plurality of initial trenches in the second direction formed through the second stack and the at least a first portion of the first stack; and
a plurality of completed trenches in the second direction formed through at least a second portion of the first stack wherein at least a partial depth of the completed trenches has exposed sidewalls without the sealing material thereon.
3. The array of claim 1 , wherein first conductive lines corresponding to the memory cells are formed by the plurality of completed trenches in the first direction.
4. The array of claim 2 , wherein the plurality of completed trenches in the second direction ends on the first conductive material corresponding to the first conductive lines.
5. The array of claim 1 , wherein the first stack includes:
an active select device material formed between a first electrode material and a second electrode material; and
an active resistive storage element material formed between the second electrode material and a third electrode material.
6. The array of claim 5 , wherein:
the active select device material, the first electrode material, and the second electrode material corresponds to an ovonic threshold switch (OTS); and
the active resistive storage element material, the second electrode material and the third electrode material correspond to a phase change storage element.
7. The array of claim 5 , wherein the first electrode material is formed in contact with the first conductive material.
8. The array of claim 7 , wherein the sealing material formed on the sidewalls of the initial trenches seal at least a portion of the active resistive storage element material.
9. The array of claim 5 , wherein the third electrode material is formed in contact with the first conductive material.
10. The array of claim 9 , wherein the sealing material formed on the sidewalls of the initial trenches seal at least a portion of the active select device material.
11. The array of claim 1 , wherein the first stack of materials includes:
an active select device material formed between a first electrode material and a second electrode material;
an active resistive storage element material formed between the second electrode material and a third electrode material; and
a second conductive material formed on the third electrode material.
12. The array of claim 1 , wherein:
the second stack of materials includes a second conductive material; and
the second trenches formed through the second stack and at least a first portion of the first stack in the second direction are formed through the second conductive material to form second conductive lines.
13. An array of memory cells, comprising:
first conductive lines formed in a first direction on a first conductive material;
second conductive lines formed in a second direction; and
a first stack of materials comprising:
memory cells formed by first trenches and located at intersections of the first conductive lines and the second conductive lines, the memory cells comprising:
a select device structure comprising an active select device material formed between a first electrode and second electrode;
a storage element comprising an active storage element material formed between the second electrode and a third electrode;
a first sealing material formed on sidewalls of one of the active select device material and the active storage element material in the second direction;
a second sealing material formed on sidewalls of the one of the active select device material and the active storage element material in the first direction; and
a second stack of materials formed on the first stack and comprising:
second trenches formed through the second stack and at least a first portion of the first stack in the second direction, wherein the second trenches comprise a third sealing material formed on sidewalls of the second trenches in the second direction.
14. The array of claim 13 , wherein the first sealing material is formed on the sidewalls of the one of the active select device material and the active storage element material in the first direction.
15. The array of claim 13 , wherein the active select device material is an ovonic threshold switch (OTS).
16. The array of claim 15 , wherein the active storage element material is a phase change material (PCM).
17. The array of claim 13 , wherein the active select device material is an ovonic threshold switch (OTS) and the active storage element material is a chalcogenide.
18. The array of claim 13 , wherein the first conductive lines are word lines and the second conductive lines are bit lines.
19. An array of memory cells, comprising:
first conductive lines formed in a first direction on a first conductive material;
second conductive lines formed in a second direction; and
a first stack of materials comprising:
resistive memory cells formed by first trenches and located at intersections of the first conductive lines and the second conductive lines, the resistive memory cells comprising:
an ovonic threshold switch (OTS);
a resistive storage element comprising a phase change material (PCM) formed between a first electrode and a second electrode, the second electrode being shared by the OTS and the resistive storage element;
a first sealing material formed on sidewalls of an active material of the OTS in the first direction; and
a second sealing material formed on sidewalls of the active material of the OTS in the second direction; and
a second stack of materials formed on the first stack and comprising:
second trenches formed through the second stack and at least a first portion of the first stack in the second direction, wherein the second trenches comprise a third sealing material formed on sidewalls of the second trenches in the second direction.
20. The array of claim 19 , wherein the first sealing material, the second sealing material, and the third sealing material formed on the sidewalls of the active material of the OTS are deposited to a thickness of not greater than about 5 nanometers by a process selected from atomic layer deposition (ALD) and conformal chemical vapor deposition (CVD).