Gate pulse modulation waveform-shaping circuit
A gate pulse modulation waveform-shaping circuit includes an input terminal, an output pair, and a gate pulse modulation waveform-shaping control circuit. The input terminal receives a control signal. The output pair is connected to a scan line for outputting a gate output voltage. The gate pulse modulation waveform-shaping control circuit is connected to the output pair for adjusting a voltage waveform on the scan line. The gate pulse modulation waveform-shaping control circuit is based on the control signal to use a time interval or fixed discharge voltage to generate a desired delay for adjusting a discharge slope thereby generating different discharge time on the scan line, so that the gate output voltage has a voltage waveform including at least two waveform segments each with a non-zero sliding slope and at least two waveform segments each with a zero slope.
1. A gate pulse modulation waveform-shaping circuit comprising:
an input terminal for receiving a control signal;
an output pair connected to a scan line for outputting a gate output voltage; and
a gate pulse modulation waveform-shaping control circuit connected to the output pair,
wherein the gate pulse modulation waveform-shaping control circuit is based on the control signal to use a time interval or a fixed discharge voltage to generate a delay for adjusting a discharge slope thereby generating different discharge time on the scan line, so that the gate output voltage has a voltage waveform, the voltage waveform including a plurality of waveform segments, the voltage waveform including at least two of the waveform segments each with a non-zero sliding slope and at least two of the waveform segments each with a zero slope.
2. The gate pulse modulation waveform-shaping circuit as claimed in claim 1 , further comprising:
a first control circuit connected to the output pair for controlling output timing and voltage value of the gate output voltage; and
a second control circuit connected to the gate pulse modulation waveform-shaping control circuit for controlling the output pair to be turned on and off.
3. The gate pulse modulation waveform-shaping circuit as claimed in claim 2 , further comprising:
a delay parameter circuit connected to the gate pulse modulation waveform-shaping control circuit for storing at least one code and using the at least one code to configure different parameters for adjusting additional delay time, in addition to a basic discharge time, thereby generating the time interval and the delay, so as to adjust the discharge slope for generating different discharge time on the scan line.
4. The gate pulse modulation waveform-shaping circuit as claimed in claim 3 , wherein the output pair includes a first PMOS transistor and a second PMOS transistor.
5. The gate pulse modulation waveform-shaping circuit as claimed in claim 4 , wherein the first control circuit is connected to the first PMOS transistor for turning on the first PMOS transistor so as to generate a rising edge of the gate output voltage.
6. The gate pulse modulation waveform-shaping circuit as claimed in claim 5 , wherein the gate pulse modulation waveform-shaping control circuit is connected to the second PMOS transistor for turning on the second PMOS transistor so as to generate a falling edge of the gate output voltage having different discharge time.
7. The gate pulse modulation waveform-shaping circuit as claimed in claim 6 , wherein the gate pulse modulation waveform-shaping control circuit further includes:
an oscillator with different selectable frequencies to generate different discharge time intervals.
8. The gate pulse modulation waveform-shaping circuit as claimed in claim 7 , wherein the falling edge of the gate output voltage includes k discharge sections, each discharge section being composed of Xk discharge and delay time intervals, each discharge and delay time interval being composed of mk discharge time intervals and nk delay time intervals, and different discharge and delay time intervals are provided with different Xk, nk, and mk values, where Xk, nk, mk, k are each a natural number.
9. The gate pulse modulation waveform-shaping circuit as claimed in claim 2 , further comprising:
a voltage difference parameter circuit for outputting different voltage differences;
a voltage difference value and voltage difference multiple generator connected to the scan line and the voltage difference parameter circuit for generating comparison voltages with different voltage values according to the voltage differences outputted by the voltage difference parameter circuit; and
a comparator connected to the scan line and the voltage difference value and voltage difference multiple generator for comparing the voltage on the scan line and the comparison voltages so as to output an indicative signal.
10. The gate pulse modulation waveform-shaping circuit as claimed in claim 9 , wherein the gate pulse modulation waveform-shaping control circuit uses the indicative signal to adjust additional delay time, in addition to a basic discharge time, so as to generate the fixed discharge voltage thereby generating the delay, such that the discharge slope is adjusted for generating different discharge time on the scan line.