Clock and data recovery for pulse based multi-wire link
A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
1. A method for decoding data at a receiving device coupled to a multi-wire interface, comprising:
at the receiving device, detecting pulses on one or more wires of the multi-wire interface;
in each of a plurality of transmission intervals:
generating an edge in a receive clock responsive to detecting a pulse on one or more wires of the multi-wire interface; and
providing a digit of a multi-digit number after the edge in the receive clock is generated in each of the plurality of transmission intervals, wherein each bit of the digit identifies whether a pulse was transmitted on one wire of the multi-wire interface during a corresponding transmission interval;
combining digits generated in the plurality of transmission intervals to obtain the multi-digit number; and
transcoding the multi-digit number to obtain received data,
wherein a pulse is transmitted on at least one wire of the multi-wire interface during each of the plurality of transmission intervals.
2. The method of claim 1 , wherein a data word is encoded in the multi-digit number.
3. The method of claim 1 , wherein the multi-wire interface comprises N wires and the multi-digit number is expressed as a base (2 N −1) number.
4. The method of claim 1 , wherein the multi-wire interface is a two-wire interface and the multi-digit number is expressed as a ternary number, or the multi-wire interface is a three-wire interface and the multi-digit number is expressed as a septenary number.
5. The method of claim 1 , further comprising:
decoding first information from return-to-zero pulse-encoded signals received from the multi-wire interface; and
decoding second information from one or more non-return-to-zero signals received from the multi-wire interface.
6. The method of claim 1 , wherein capacitively-coupled signals are received from the multi-wire interface.
7. The method of claim 1 , wherein inductively-coupled signals are received from the multi-wire interface.
8. The method of claim 1 , wherein optically-coupled signals are received from the multi-wire interface.
9. The method of claim 1 , wherein generating the edge in the receive clock comprises:
combining pulses received on the one or more wires into a combination signal; and
delaying the combination signal to provide the receive clock.
10. The method of claim 1 , wherein generating the edge in the receive clock comprises:
combining pulses received on the one or more wires into a combination signal;
providing the combination signal to one-shot logic that is configured to produce a fixed-duration pulse responsive to an edge in the combination signal; and
delaying the fixed-duration pulse to provide a pulse in the receive clock.