IP Library Granted Patent US 9,625,963
Granted Patent B2
US 9,625,963 · App. 14/836,572 · Granted Apr 18, 2017

Thermally-constrained voltage and frequency scaling

Inventors: Rajat Mittal (San Diego, CA); Mehdi Saeidi (San Diego, CA)
Assignee: QUALCOMM Incorporated
G06F1/206G06F1/324G06F1/3234G06F1/3296H03K19/0008
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Quick Facts
Patent No.
US 9,625,963
App. No.
14/836,572
Granted
Apr 18, 2017
Kind
B2
Abstract

A performance setting technique is disclosed for a clocked circuit such as a processor in an integrated circuit. The technique determines a maximum power consumption for the clocked circuit as a function of a total thermal resistance of a mobile device incorporating the integrated circuit. The total thermal resistance is a sum of a system thermal resistance for the mobile device and a device thermal resistance for the integrated circuit.

Claims (34)

1. A method, comprising:

summing a system thermal resistance for a system including an integrated circuit having a clocked circuit and a device thermal resistance for the integrated circuit to determine a total thermal resistance for the system, wherein the system includes a housing surrounding the integrated circuit, and wherein the system thermal resistance depends upon a thermal conductivity of the housing and is independent of the device thermal resistance for the integrated circuit;

determining a maximum power consumption for the clocked circuit responsive to the total thermal resistance for the system;

determining a performance setting for the clocked circuit that does not exceed the maximum power consumption at the thermal limit, wherein the clocked circuit comprises a processor, and wherein the determined performance setting comprises a power supply voltage setting for the processor; and

configuring the processor to operate according to the determined performance setting.

2. The method of claim 1 , wherein the determined performance setting further comprises a clock frequency for the processor.

3. The method of claim 1 , wherein the total thermal resistance for the system is defined with regard to a location in the system receiving the integrated circuit.

4. The method of claim 3 , wherein the total thermal resistance for the system is defined with regard to a circuit board location in the system that receives the integrated circuit as a system on a chip (SOC).

5. The method of claim 1 , further comprising:

determining a plurality of performance curves for the processor, each performance curve identifying a power consumption for the processor as a function of a temperature for the processor, each performance curve corresponding to a unique performance setting for the processor; and

identifying from the plurality of performance curves, a selected performance curve that does not exceed the maximum power consumption at the thermal limit, wherein the determined performance setting comprises the performance setting for the selected performance curve.

6. The method of claim 5 , wherein each performance setting comprises a unique pair of a power supply voltage setting and clock frequency for the processor.

7. An apparatus, comprising:

a memory for storing instructions; and

a first processor configured to execute the stored instructions, wherein the stored instructions upon execution by the first processor cause the first processor to:

sum a system thermal resistance for a mobile device including an integrated circuit having a second processor and a device thermal resistance for the integrated circuit to determine a total thermal resistance for the mobile device, wherein the mobile device includes a housing surrounding the integrated circuit, and wherein the system thermal resistance depends upon a thermal conductivity of the housing and is independent of the device thermal resistance for the integrated circuit;

determine a maximum power consumption for the second processor responsive to the total thermal resistance;

determine a performance setting for the second processor that does not exceed the maximum power consumption at the thermal limit, wherein the determined performance setting comprises a power supply voltage setting for the second processor; and

configure the second processor to operate according to the determined performance setting.

8. The apparatus of claim 7 , wherein the second processor comprises a system on a chip (SOC).

9. The apparatus of claim 8 , wherein the determined performance setting further comprises a clock frequency for the SOC.

10. The apparatus of claim 8 , wherein the total thermal resistance of the mobile device is defined with regard to a space on a circuit board that receives the SOC and with regard to a device thermal resistance for the SOC.

11. The apparatus of claim 10 , wherein the mobile device comprises a cellular telephone.

12. A non-transitory computer readable medium having computer-readable instructions stored thereon, wherein the computer-readable instructions when executed by a processor cause the processor to:

sum a system thermal resistance for a mobile device including an integrated circuit having a microprocessor and a device thermal resistance for the integrated circuit to determine a total thermal resistance for the mobile device, wherein the mobile device includes a housing surrounding the integrated circuit, and wherein the system thermal resistance depends upon a thermal conductivity of the housing and is independent of the device thermal resistance for the integrated circuit;

determine a maximum power consumption for the microprocessor responsive to a the total thermal resistance;

determine a performance setting for the microprocessor that does not exceed the maximum power consumption at the thermal limit, wherein the determined performance setting comprises a power supply voltage setting for the microprocessor; and

configure the microprocessor to operate according to the determined performance setting.

13. The non-transitory computer readable medium of claim 12 , wherein the determined performance setting further comprises a clock frequency for the microprocessor.

14. The non-transitory computer readable medium of claim 12 , wherein the total thermal resistance for the mobile device is defined with regard to a location in the mobile device receiving the integrated circuit.

15. The non-transitory computer readable medium of claim 12 , wherein the total thermal resistance for the mobile device is defined with regard to a circuit board location in the mobile device that receives the integrated circuit as a system on a chip (SOC).

16. The non-transitory computer readable medium of claim 13 , wherein the computer-readable instructions when executed by the processor further cause the processor to:

determine a plurality of performance curves for the microprocessor, each performance curve identifying a power consumption for the microprocessor as a function of a temperature for the microprocessor, each performance curve corresponding to a unique performance setting for the microprocessor; and

identify from the plurality of performance curves, a selected performance curve that satisfies the maximum power consumption at the thermal limit, wherein the determined performance setting for the microprocessor comprises the performance setting for the selected performance curve.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2015
From: MITTAL, RAJAT; SAEIDI, MEHDI
To: QUALCOMM INCORPORATED
Reel/Frame 036960/0151 →
Continuity (2)
Provisional Application 62043716 · Aug 29, 2014
Related Publication 20160062422A1 · Mar 3, 2016