Multilayered ceramic capacitor and board for mounting the same
There is provided a multilayered ceramic capacitor including: a ceramic body in which a plurality of dielectric layers are stacked; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance; an upper cover layer formed above the active layer, a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes formed to cover both end surfaces of the ceramic body, wherein a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9.
1. A multilayered ceramic capacitor comprising:
a ceramic body in which a plurality of dielectric layers are stacked;
an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance;
an upper cover layer formed above the active layer;
a lower cover layer formed below the active layer and being thicker than the upper cover layer; and
first and second external electrodes formed to cover the both end surfaces of the ceramic body,
wherein a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9, and
when half of a total thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, half of a total thickness of the active layer is defined as C, and a thickness of the upper cover layer is defined as D, a ratio ((B+C)/A) of deviation between a center of the active layer and a center of the ceramic body is in a range of 1.063 to 1.745 (1.063≦(B+C)/A≦1.745).
2. The multilayered ceramic capacitor of claim 1 , wherein a ratio (D/B) of the thickness D of the upper cover layer to the thickness B of the lower cover layer is in a range of 0.021 to 0.422 (0.021≦D/B≦0.422).
3. The multilayered ceramic capacitor of claim 1 , wherein a ratio (B/A) of the thickness B of the lower cover layer to the half A of the total thickness of the ceramic body is in a range of 0.329 to 1.522 (0.329≦B/A≦1.522).
4. The multilayered ceramic capacitor of claim 1 , wherein a ratio (CB) of the half C of the total thickness of the active layer to the thickness B of the lower cover layer is in a range of 0.146 to 2.458 (0.146≦C/B≦2.458).
5. The multilayered ceramic capacitor of claim 1 , wherein points of inflection (PI) formed in the both end surfaces of the ceramic body are formed in positions lower than a center of the ceramic body in a thickness direction due to a difference between strain generated in a center of the active layer and strain generated in the lower cover layer when voltage is applied thereto.
6. A board for mounting a multilayered ceramic capacitor, the board comprising:
a printed circuit board having first and second electrode pads formed thereon; and
a multilayered ceramic capacitor mounted on the printed circuit board,
wherein the multilayered ceramic capacitor includes:
a ceramic body in which a plurality of dielectric layers are stacked;
an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance;
an upper cover layer formed above the active layer;
a lower cover layer formed below the active layer and being thicker than the upper cover layer; and
first and second external electrodes formed on the both end surfaces of the ceramic body and connected to the first and second electrode pads by soldering,
a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9, and
when half of a total thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, half of a total thickness of the active layer is defined as C, and a thickness of the upper cover layer is defined as D, a ratio ((B+C)/A) of deviation between a center of the active layer and a center of the ceramic body is in a range of 1.063 to 1.745 (1.063≦(B+C)/A≦1.745).
7. The board of claim 6 , wherein a ratio (D/B) of the thickness D of the upper cover layer to the thickness B of the lower cover layer is in a range of 0.021 to 0.422 (0.021≦D/B≦0.422).
8. The board of claim 6 , wherein a ratio (B/A) of the thickness B of the lower cover layer to the half A of the total thickness of the ceramic body is in a range of 0.329 to 1.522 (0.329≦B/A≦1.522).
9. The board of claim 6 , wherein a ratio (CB) of the half C of the total thickness of the active layer to the thickness B of the lower cover layer is in a range of 0.146 to 2.458 (0.146≦C/B≦2.458).
10. The board of claim 6 , wherein points of inflection (PI) formed in the both end surfaces of the ceramic body are formed in positions lower than a height of the soldering due to a difference between strain generated in a center of the active layer and strain generated in the lower cover layer when voltage is applied thereto.