IP Library Granted Patent US 9,627,268
Granted Patent B2
US 9,627,268 · App. 14/884,746 · Granted Apr 18, 2017

Method for fabricating semiconductor device

Inventors: Ching-Yu Chang (Taipei, TW); Li-Wei Feng (Kaohsiung, TW); Shih-Hung Tsai (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Jyh-Shyang Jenq (Pingtung County, TW); Chien-Ting Lin (Hsinchu, TW); Yi-Ren Chen (Kaohsiung, TW); Shou-Wei Hsieh (Hsin-Chu, TW); Hsin-Yu Chen (Nantou County, TW); Chun-Hao Lin (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/823814H01L21/324H01L21/823821H01L21/823878
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,627,268
App. No.
14/884,746
Granted
Apr 18, 2017
Kind
B2
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Claims (15)

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region;

forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;

forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure so that each of the first fin-shaped structure and the second fin-shaped structure is divided into a top portion and a bottom portion;

forming a first doped layer on the STI and on the top portion of the second fin-shaped structure;

forming a second doped layer on the STI and the top portion of the first fin-shaped structure, wherein the first doped layer and the second doped layer comprise dopants of same type; and

performing an anneal process.

2. The method of claim 1 , further comprising:

forming the first doped layer and a first liner on the STI, the first fin-shaped structure, and the second fin-shaped structure;

removing the first liner and the first doped layer from the first region;

forming the second doped layer on the STI, the first fin-shaped structure, and the first liner; and

performing the anneal process.

3. The method of claim 1 , wherein the dopant concentration of the first doped layer is higher than the dopant concentration of the second doped layer.

4. The method of claim 1 , wherein the first doped layer and the second doped layer comprise borosilicate glass (BSG).

5. The method of claim 1 , wherein the first doped layer and the second doped layer comprise phosphosilicate glass (PSG).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2015
From: CHANG, CHING-YU; FENG, LI-WEI; TSAI, SHIH-HUNG; FU, SSU-I; JENQ, JYH-SHYANG; LIN, CHIEN-TING; CHEN, YI-REN; HSIEH, SHOU-WEI; CHEN, HSIN-YU; LIN, CHUN-HAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036805/0768 →
Priority Claims (1)
TW 104129113 A · Sep 3, 2015 · national
Continuity (1)
Related Publication 20170069543A1 · Mar 9, 2017