Thinning in package using separation structure as stop

1. A method of forming a thinned encapsulated chip structure, the method comprising:

forming a separation master structure arranged within a wafer; and

singularising the wafer with its separation master structure into an electronic chip with its separation structure being formed by a portion of the separation master structure, and into at least one further electronic chip each having a further separation structure being formed by another portion of the separation master structure;

encapsulating part of the electronic chip by an encapsulating structure;

thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

2. The method according to claim 1 , further comprising, before the singularising, forming integrated circuit elements in a portion of the wafer being separated by the separation master structure from another portion of the wafer so that, after the singularising, each of the electronic chip and the at least one further electronic chip comprises at least one of the integrated circuit elements.

3. The method according to claim 2 , further comprising, before the forming of the integrated circuit elements, epitaxially growing an additional body to form part of the portion of the wafer being separated by the separation master structure from the other portion of the wafer, wherein the integrated circuit elements are formed at least partially in the additional body.

4. The method according to claim 1 , wherein the electronic chip is laterally surrounded by the encapsulating structure and one of two opposing main surfaces of the electronic chip is covered at least partially by the encapsulating structure, whereas the other one of the two opposing main surfaces remains exposed to an environment.

5. The method according to claim 1 , wherein the method comprises selectively removing the separation structure after the thinning.

6. The method according to claim 1 , wherein the method comprises providing the electronic chip with at least one integrated circuit element in a portion of the electronic chip being separated by the separation structure from another portion of the electronic chip being removed by the thinning.

7. The method according to claim 1 , wherein the thinning is performed by back etching material of the electronic chip while using the encapsulating structure as an etch mask.

8. The method according to claim 1 , wherein the method further comprises:

providing a further separation structure arranged within a further electronic chip;

encapsulating part of the further electronic chip by the encapsulating structure together with the electronic chip; and

thinning selectively the further electronic chip partially encapsulated by the encapsulating structure together with the electronic chip so that the encapsulating structure remains with a larger thickness than the thinned further electronic chip, wherein the further separation structure functions as a thinning stop.

9. The method according to claim 8 , wherein the separation structure and the further separation structure are formed at the same height level.

10. The method according to claim 8 , comprising singularising sections each comprising a respective one of the thinned electronic chips encapsulated by a respective portion of the encapsulating structure.

11. A method of forming a thinned encapsulated semiconductor device, the method comprising:

forming, on a wafer level, a separation layer being formed by a portion of a separation master structure within a semiconductor chip forming part of the wafer so that the separation layer separates a first chip body of the semiconductor chip on one side of the separation layer with regard to a second chip body of the semiconductor chip on the other side of the separation layer;

forming, on the wafer level, at least one integrated circuit element in and/or on the first chip body;

singularising the wafer with its separation master structure into the electronic chip with its separation structure being formed by a portion of the separation master structure, and into at least one further electronic chip each having a further separation structure being formed by another portion of the separation master structure;

encapsulating part of the singularised chip by an encapsulating structure;

removing selectively the second chip body up to the separation layer so that the encapsulating structure remains with a larger thickness than the first chip body.

12. The method according to claim 11 , wherein the first chip body is formed with a thickness of less than 10 μm.

13. The method according to claim 11 , wherein the method comprises, on the wafer level, forming an additional body on the first chip body.