Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
1. A method of forming fin field-effect transistor (FET) devices, the method comprising the steps of:
patterning fins in a wafer;
forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant;
forming the dummy gates over portions of the fins that serve as channel regions of the finFET device;
forming spacers on opposite sides of the dummy gates;
depositing a gap fill oxide on the wafer, filling any gaps between the spacers;
removing the dummy gates forming gate trenches;
trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and
forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
2. The method of claim 1 , wherein the doped epitaxial cladding layer comprises epitaxial silicon, germanium, or silicon germanium.
3. The method of claim 1 , wherein the step of trimming the fins within the gate trenches removes at least a portion of the doped epitaxial cladding layer from the fins within the gate trenches.
4. The method of claim 1 , wherein the width of the fins outside of the gate trenches is from about 7 nanometers to about 20 nanometers, and ranges therebetween.
5. The method of claim 1 , wherein the width of the fins within the gate trenches is from about 3 nanometers to about 10 nanometers, and ranges therebetween.
6. The method of claim 1 , wherein the dummy gates comprise poly-silicon.
7. The method of claim 1 , wherein the step of forming the replacement gate stacks comprises the steps of:
depositing a conformal gate dielectric material into and lining the gate trenches and covering the fins;
depositing a conformal workfunction setting metal layer into the gate trenches on the conformal gate dielectric; and
depositing a filler gate metal into and filling the gate trenches.
8. The method of claim 7 , wherein the conformal gate dielectric includes a high-κ material selected from the group consisting of hafnium oxide and lanthanum oxide.
9. The method of claim 7 , wherein the conformal workfunction setting metal layer comprises an n-type workfunction metal selected from the group consisting of: titanium nitride, tantalum nitride, and aluminum-containing alloys.
10. The method of claim 7 , wherein the conformal workfunction setting metal layer comprises a p-type workfunction metal selected from the group consisting of: titanium nitride, tantalum nitride, and tungsten.
11. The method of claim 7 , wherein the filler gate metal comprises tungsten or aluminum.
12. The method of claim 1 , further comprising the step of:
using a fin hardmask to pattern the fins in the wafer.
13. The method of claim 12 , further comprising the step of:
removing the fin hardmask from the fins prior to forming the dummy gates.
14. The method of claim 12 , further comprising the steps of:
trimming the fin hardmask prior to trimming the fins; and
removing the fin hardmask after trimming the fins.
15. A method of forming fin FET devices, the method comprising the steps of:
patterning fins in a wafer using a fin hardmask;
forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant;
forming the dummy gates over portions of the fins that serve as channel regions of the finFET device;
forming spacers on opposite sides of the dummy gates;
depositing a gap fill oxide on the wafer, filling any gaps between the spacers;
removing the dummy gates forming gate trenches;
trimming the fin hardmask to a width smaller than a patterned width of the fins prior to trimming the fins;
trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches;
removing the fin hardmask after trimming the fins; and
forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.