Method for metal gate surface clean
The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H 3 PO 4 solution.
1. A method comprising:
providing a metal gate with a material layer disposed thereover;
removing a portion of the material layer to form a trench, a surface of the metal exposed in the trench being oxidized to form a first oxide layer on the metal gate;
removing the first oxide layer;
forming a second oxide layer on the metal gate; and
reducing the second oxide layer to a metal included in the metal gate using a reducing agent.
2. The method of claim 1 , further comprising forming a dielectric layer over the material layer prior to removing the portion of the material layer to form the trench.
3. The method of claim 2 , wherein removing the portion of the material layer to form the trench includes removing a portion of the dielectric layer.
4. The method of claim 3 , wherein removing the portion of the material layer to form the trench includes performing a first etching process, and
wherein removing the portion of the dielectric layer includes performing a second etching process that is different than the first etching process.
5. The method of claim 4 , wherein the first etching process includes performing a wet etching process and wherein the second etching process includes performing a dry etching process.
6. The method of claim 1 , wherein the material layer includes an etch stop layer.
7. The method of claim 1 , further comprising:
forming a dielectric layer over a substrate, wherein the metal gate is disposed within the dielectric layer; and
forming a conductive feature over the substrate, wherein the conductive feature is disposed within the dielectric layer such that the conductive feature is separated from the metal gate by the dielectric layer, and
wherein a surface of the conductive feature is exposed within the trench.
8. The method of claim 7 , wherein the conductive feature is one of a metal contact, a metal via, and a metal line.
9. A method comprising:
forming a metal gate over a semiconductor substrate;
forming a first material layer over the metal gate;
removing the first material layer to expose the metal gate;
forming a first oxide layer on the exposed metal gate;
removing the first oxide layer;
forming a second oxide layer on the metal gate; and
reducing the second oxide layer to a metal included in the metal gate using a reducing agent.
10. The method of claim 9 , wherein removing the first oxide layer includes performing a wet etching process.
11. The method of claim 9 , further comprising performing a thermal treatment process on the metal gate after removing the first oxide layer and before reducing the second oxide layer to the metal included in the metal gate using the reducing agent.
12. The method of claim 9 , further comprising performing a plasma treatment process on the metal gate after reducing the second oxide layer to the metal included in the metal gate using the reducing agent.
13. The method of claim 9 , further comprising forming a contact structure over the metal gate such that the contact structure interfaces with the metal gate.
14. The method of claim 9 , further comprising forming a second material layer over the first material layer that is different than the first material layer, and
wherein removing the first material layer to expose the metal gate includes removing the second material layer.
15. A method comprising:
forming a metal gate over a semiconductor substrate;
forming a first material layer over the metal gate;
forming a trench through the first material layer to expose the metal gate;
forming a first oxide layer on the exposed metal gate;
removing the first oxide layer;
forming a second oxide layer on the metal gate; and
reducing the second oxide layer to a metal included in the metal gate using a reducing agent.
16. The method of claim 15 , further comprising performing a plasma treatment process to expand the width of the trench.
17. The method of claim 16 , further comprising:
forming a barrier layer in the expanded trench; and
forming a conductive material over the barrier layer in the expanded trench.
18. The method of claim 15 , further comprising forming a conductive feature over the semiconductor substrate, and
wherein forming the trench through the first material layer to expose the metal gate includes forming the trench through the first material layer to expose the conductive feature.
19. The method of claim 18 , wherein the conductive feature remains exposed within the trench during the removing of the first oxide layer and the reducing of the second oxide layer to the metal included in the metal gate using the reducing agent.
20. The method of claim 15 , wherein removing the first oxide layer includes applying a H 3 PO 4 solution, and
wherein reducing the second oxide layer includes applying a nitrogen/hydrogen (N 2 /H 2 ) plasma treatment process.